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The questions you are posting indicate you have some goal in mind and you are trying to figure out how to accomplish it. Why don't you just tell us what it is you are trying to do and then we can advise you on how to do it.
Jake
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I am trying to add a cache coherence protocol in a multicore Nios II processor system on Altera DE2 board. At least two processors share a off-chip SDRAM. When one processor have a write action to his individual data cache, the action should be visiable to others. That need a snooping transcation to other processors, that processor needs a slave port.
Between the SDRAM controller and the system interconnect fabric, I want to add a register which contains both master and slave ports so as to initiate snooping transaction to processors also.
Is this clear?
Hopes :)
