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Can you simulate AHDL with Modelsim?

Altera_Forum
Honored Contributor II
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Hi, 

 

My application is not written in VHDL or Verilog because at my company we have loads and loads of legacy AHDL. I just loaded Quartus 11.0 and Modelsim.  

 

I have used Modelsim in the past to simulate VHDL files but just realized that I don't know how to create a testbench in VHDL for an AHDL file. Is such a thing possible to do? 

 

I hope that I don't have to go back to something like Altera version 9.0. 

 

Thank You 

Tom
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Altera_Forum
Honored Contributor II
494 Views
Altera_Forum
Honored Contributor II
494 Views

I fully understand your legacy AHDL problem - I have had exactly the same. 

 

Best thing to do - get a boss who sympathises and make sure all new designs use VHDL. Then try and avoid any legacy work! If they keep insisting that AHDL is the way forward - find a new job!
Altera_Forum
Honored Contributor II
494 Views

I started my HDL carrier with ABEL 15 years back. Those days even counters were laid down manually with flip-flops. We changed loyalty to Altera and hence a shift from ABEL to AHDL.  

ADHL was adorable. There was no big conceptual difference from ABEL, but reusing counters, comparators was saving lots of work and as chip densities grew our code sizes grew too and we had no difficulty growing up. 

For the last project we were advised that Altera was depreciating AHDL and we needed to shift to perphaps Verilog. It was a sad movement.  

Learning Verilog was not entirely easy. The syntax was confusing. For an "gates guy" thinking in terms of flip-flops and gates, the "high level" of Verilog was pretty unnatural and difficult. 

 

Thank goodness, we did not do anything drastic like running a Xilinx convertor on AHDL, or strating from scratch using verilog. 

We decided to do only new modules in Verilog. 

But as project progressed we decided that modules with complex alogs be in AHDL and we have some wrapper. 

And lol at the end there were only two places we used Verilog. 1. To create an interface from SoPC to our logic 2. Test bench for simulation in Modelsim. Recently even (1) was removed when Qsys entered! Had there been a vector waveform input option for Modelsim net writer even (2) would have been avoided! But had the wonderful native simulator been supported would it not been marvellous. 

 

We use the latest Quartus edition, the latest FPGA, the latest Nios suite and the unrelenting language AHDL. 

The support that Altera continues to provide for AHDL is the reason for all feat which we are proud of and I pray Altera continues to keep this wonderful language glorious. 

 

Ravi
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