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Hi,
In the Altera manual, it talked about Timing Driven Synthesis as below: "The Timing-Driven Synthesis logic option specifies whether Analysis & Synthesis should use the SDC timing constraints of your design to better optimize the circuit." Does it mean if I don't turn on this option, the compiler would just ignore the sdc file while synthesizing and compilation? And everything that I did for the timing constraints in TimeQuest is just useless? And is it suggested to turn on this option? Thanks a lot.Link Copied
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Hi,
The answer is no. There two stages. synthesis and fitting. You can set synthesis on or off but fitting will always use sdc. I noted from my work that turning synthesis off is better for resource and speed... ! why? needs answer.- Mark as New
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I think turning on Timing Driven Synthesis doesn't necessarily mean larger area. It depends on the sdc constraint file and the specific design.
And the three synthesis orientation options: Area, Balanced and Speed will also affect how Timing Driven work. Anyway, I don't have enough experiences to know in which circumstances should I turn on this option.- Mark as New
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There isn't much reason to have it off. It was an option when it was new(a few years ago) and may have had issues like slower synthesis times. It should be on.
Note that timing driven synthesis didn't make designs much faster, as setting synthesis to speed generally already did all the speed algorithms. Instead it allows the fitter to find things that don't need speed and synthesize them for area.- Mark as New
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It is an option still. If it suits the design whichever way then why not, common sense. I have designs done by Altera (subcontracted) and they opted to turn it off.
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True. In theory it should always be on, as the trade-offs are small(it shouldn't increase run-time very much and should give better results), but there are always corner cases.
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