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Altera_Forum
Honored Contributor I
1,097 Views

Cannot change $now in tcl?

Hello, 

 

I tried to change $now back and forth in time by like: 

set now 1800 

which seemed to have worked temporarily in the sense that one can  

puts "$now" 

and see 1800. 

 

But after  

run 50 

it changes back to the last simulation time value. 

 

Question: Does it internally has a copy so that the actual value of $now can never be changed? 

 

 

greg
0 Kudos
4 Replies
Altera_Forum
Honored Contributor I
34 Views

In VHDL (I don't know about Verilog) now holds the current simulation time, I think tcl now is a copy of that.

Altera_Forum
Honored Contributor I
34 Views

I wonder not know if such jumping is possible. 

 

1.  

If one programs in assembly language or C, advancing the program counter register to a future value could have unexpected consequences such as corrupting the stack. MS Visual Studio allows mouse dragging the line indicator in C++/VB/C# functions to change back/forth PC location to ease debugging, but under the hood they added lots of auxiliary metadata management to the compiler to enable that. It is not impossible but just difficult. 

 

I want to know if Modelsim supports changing the essential "now". Anyway it is a mature (more than two decades) software and the most widely used HDL simulator. I don't know if they have built this into the software. 

 

 

 

 

2.  

 

--- Quote Start ---  

In VHDL (I don't know about Verilog) now holds the current simulation time, I think tcl now is a copy of that. 

--- Quote End ---  

 

I saw you and Tricky in another thread (https://www.alteraforum.com/forum/showthread.php?t=58437&p=237672#post237672) all used VHDL example, and you referred to an limitation of verilog in this one. Does Altera or IC professionals consider verilog incomplete and amateurish, some how like C++ programmers viewing javascript? For example, if we were to write the digital part of some mixed-signal block, say sampling from comparator output, for and ADC, does it feel like that VHDL is better suited, since it is more verbose and gives more direct and strict access to logic elements? 

 

 

greg
Altera_Forum
Honored Contributor I
34 Views

 

--- Quote Start ---  

I wonder not know if such jumping is possible. 

 

1.  

I want to know if Modelsim supports changing the essential "now". Anyway it is a mature (more than two decades) software and the most widely used HDL simulator. I don't know if they have built this into the software. 

 

--- Quote End ---  

 

You want timetravel, that's still a bit tricky in the real world. If you want to change the viewpoint, you need to check the reference of the wave subcommands. 

 

 

 

--- Quote Start ---  

 

2.  

 

I saw you and Tricky in another thread (https://www.alteraforum.com/forum/showthread.php?t=58437&p=237672#post237672) all used VHDL example, and you referred to an limitation of verilog in this one.  

--- Quote End ---  

 

I use VHDL since that's what I was thaught in university. My Verilog expertise is not great i.e. I can read and understand what's going on, but I don't know the finesses of the language and never had a reason to learn it (yet). From what I understand from people used Verilog learning/writing VHDL is that they prefer Verilog. As to why I use VHDL in my answers, think of HDL land as Belgium, one country two languages. If you meet someone in the street in Brussels (where they use both languages) which language do you use if you don't know which is spoken by the other? I would default to the language that I know, in HDL land that is VHDL, so I have nothing against using Verilog.
Altera_Forum
Honored Contributor I
34 Views

I got it, thanks for answer.

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