Hi All,I am using Quartus Prime v18.0 and generated PLL IP v18.0. I have successfully generated the PLL and added into the project but when I tried to modify it in the IP components, the MegaWizard failed to launch, below is the complete message of the problem. "Failed to launch MegaWizard Plug-In Manager. PLL Intel FPGA IP v18.0 could not be found in the specified library paths." See attachment for the screenshot. I tried other IP components, like FIFO, ALTLVDS_RX, ALTLVDS_TX, ALTCLKCTRL, all of it works fine. Quartus Prime: Version 18.0.0 Build 614 04/24/2018 SJ Standard Edition Target Device: Arria V GX (5AGXBB3D4F35I5) Machine: Windows 10 Pro 64bit Also, I tried the same thing on other PC (Windows 7) but the problem is the same. Need help to fix this issue. Thank You. Zeahr
Hi Zeahr,Thank you for your efforts, I replicated the issue & got the same “library paths” issue. We will come back soon. Best Regards Vikas Jathar (This message was posted on behalf of Intel Corporation)
I'm having the same problem with "Triple-Speed Ethernet" core. I used to be able to edit the core in a number of ways including opening the EMAC.vhd file generated by the wizard (attached) or double-clicking on the core in "IP Components" view.I'm on Windows 7 and using "Quartus 18.0 Standard". This was a project that worked fine in Rev 17.1. When I opened it, it asked to upgrade IP components. That feature seems broken as well since "Perform Automatic Upgrade" etc were greyed out and the only option available was close. Without a workaround, this essentially makes 18.0 unusable. https://www.alteraforum.com/forum/attachment.php?attachmentid=15534
I have the same problem. My current project was upgraded from 16.1. But, I don't think the upgrade matters. I created a new PLL. Creation seems to be okay. But, afterwards you can not edit the PLL. This is a Cyclone V GX. Running on Windows 8.1.Painful time consuming workaround is to open the top ".v" file of the PLL. Save the "Retrieval info:" from that file. Remove the old generated IP. Generate new IP from the IP Catalog while manually reading the "Retrieval Info:" to determine GUI settings. In other words, I have not found a way to edit PLL Intel FPGA IP after it is generated. (I wonder if this is due to renaming stuff from Altera to Intel.) Hope there is a fix soon.
This may be a bug caused by an incorrect replacement of the Altera name by Intel in the ip library.Until this is fixed, I could fix this like this: > locate the .lst file of the missing IP in your IntelFGPA program directory, for example for the missing PLL, locate: "pll_wizard.lst" > Change the text: "<ALIAS>Altera PLL v18.0</ALIAS> " (and higher version numbers) to: "<ALIAS>PLL Intel FPGA IP v18.0</ALIAS>" I hope this helps you also for the other IPs. Due to all documentation update notices due to the Altera -> Intel re-branding, it is hard to see the real improvements that are being made...
Thank you schendel.Changing the alias name of the IP in the .lst file does fix the issue. Thanks for the solution. I started with "root_wizard.lst" and followed a few of the other paths to the individual IP's .lst files. It looks like Intel has not had anybody go through and scrub the all <IP name>.lst files, yet. Sure would have been easier to just leave everything "Altera" and call PSG something like Intel's Altera Group or just Intel/Altera.
--- Quote Start --- This may be a bug caused by an incorrect replacement of the Altera name by Intel in the ip library. Until this is fixed, I could fix this like this: > locate the .lst file of the missing IP in your IntelFGPA program directory, for example for the missing PLL, locate: "pll_wizard.lst" > Change the text: "<ALIAS>Altera PLL v18.0</ALIAS> " (and higher version numbers) to: "<ALIAS>PLL Intel FPGA IP v18.0</ALIAS>" I hope this helps you also for the other IPs. Due to all documentation update notices due to the Altera -> Intel re-branding, it is hard to see the real improvements that are being made... --- Quote End --- That seems to work. It looks like the ALIAS in the .lst file must be edited to match the generated core. In my case, I have a file MAIN_PLL.vhd that I opened in Pre 18.0 in order to start the wizard. At the top it has:
-- megafunction wizard: %PLL Intel FPGA IP v18.0%which matches what you said to change the ALIAS to.
schendel,It also worked for the TSE. It was a bit different in that it did not have an ALIAS at all for v18.0 so I just added: <ALIAS>Triple-Speed Ethernet Intel FPGA IP v18.0</ALIAS> and it now works. The contents of the ALIAS were taken from the first line of the generated .vhd file for the core. Thanks again.
October, 2018 - This is still a problem in 18.1, although luckily the solution described above works. For the file pll_wizard.lst specifically, I search-and-replaced all occurrences of the string
PLL Intel FPGA IP
Quartus now opens the IP Component appropriately.
Intel: What's up?
Hello I too am having issues similar to those mentioned above.
I cannot find the specified library path after upgrading from 16.1 to 18.1 for the Native PHY IP.
There does not seem to be a .lst file located in the ip generated directory.
I did a search in the product folder and nothing came up.