Cannot get aclr to work

[Altera_Forum]

I'm curious to know the Quartus definition for an asynchronous clear input. When I add an aclr input to an lpm_compare megafunction I am expecting to see the output(s) clear (switch to low) when the aclr pin is asserted. Because the input is asynchronous, I expect to see the output clear regardless of the state of any other inputs. But I don't see any behavioral change from the megafunction with an asserted aclr. Is anyone using aclr pins successfully in your designs? If so, what might you suggest I look into?

[Altera_Forum]

I wonder what you checked here. aclr is only present, if a pipelined version of lpm_compare is specified.  

Then it feeds the clear inputs of all pipeline registers, as expectable.

[Altera_Forum]

I selected to pipeline the function with an output latency of one clock cycle. Then I selected to create an asynchronous clear input. I wish to use this input to clear the compare output when I want to reset the device. 

 - Then in the simulator I am raising the aclr pin. But I don't see the output clear. I only see the aeb output change states if the data inputs don't match when they are clocked.

[Altera_Forum]

I only checked the technology map, aclr is obviously connected to the aeb DFF asynchronous clear. I synthesized for Cyclone III.

[Altera_Forum]

To anthony_b_mcdonald 

Have you checked the polarity of the reset signal? Is it positive-active or negative-active? Sometimes weird problems show up when we make simple mistakes.

[Altera_Forum]

FvM, I see what you mean. In the technology map alcr is !CLR. Also, when I look deeper into the results of the simulator, I see that aclr is setting the output. So ... Altera's definition for aclr is really to asynchronously set the output. It's good to know what's happening, it's just confusing that positive logic is used for the lpm_compare output logic (aeb, aneb, agb, etc) yet negative logic is set on the output when the output is cleared.