Cannot see internal signals in ModelSim

[CZHE0]

I'm launching my verilog testbench through Quartus 18.1.0 (Tools -> Run Simulation Tool -> RTL Simulation), which opens up ModelSim 10.5b SE. I go through the following steps:

1) Compile my testbench verilog file.

2) Double click it in the work directory in Library window.

In the Objects window, I only see inputs and outputs, but no internal signals.

After doing some googling, it seems they may have been optimized out and that I need to play around with the vopt argument. I've tried setting VoptFlow = 0 in the modelsim.ini file, as well as re-running these commands in the Transcript window:

vsim -novopt work.my_tb

vsim -voptargs="+acc" work.my_tb

Unfortunately none of this made a difference and I still cannot see internal signals in the Objects window.

What am I missing?

[AnandRaj_S_Intel]

Hi Colin,

Okay,

1. Try by deleting the work folder and disabling optimization option in the ModelSim compilation option. (disable in both Verilog and VHDL tab).
2. Also try by add VoptFlow = 0 in modelsim.ini.

we can see all the signals in the wave window by selecting all items in the design.

If still, you can't see internal signals. I recommend that you ask in the Mentor Forum.

Regards

Anand

[CZHE0]

Hi Anand,

I've tried your suggestions but I still cannot see any internal signals. I will post this question in the Mentor community forum.

Thanks.