Hi
I have a add in verilog to add 2 times 4 bit A+B and a carry to get a result of 4 bit + 1 carry out
I do use Quartus 14.0 and a MAX10
I do have this verilog code:
module add_4bit_carry( Ai,Bi,cin, Fo,cout);
input [3:0] Ai;
input [3:0] Bi;
input cin;
output [3:0] Fo;
output cout;
wire [4:0] total;
assign total=Ai+Bi+cin;
assign Fo=total[3:0];
assign cout=total[4];
endmodule
When I see the RTL I.m very surprised the CIN are not connected to the Carry in on the first adder ... I see no why Quartus do use 2 adders.
I want to save LUT's and to have a high Fmax so how to force the CIN to be used?
http://www.alteraforum.com/forum/attachment.php?attachmentid=11006&stc=1
