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Simulation of a qsys system with sdram in vhdl

Altera_Forum
Honored Contributor II
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Hello, 

 

i want to simulate a qsys system with sdram in vhdl. If i try to simulate it, the simulation stops with message that a component is missing. 

 

niosii_system_nios2_instruction_master_translator_ avalon_universal_master_0_agent.vho 

 

In the thread qsys simulation error when using vhdl testbench simulation model (http://www.alteraforum.com/forum/showthread.php?t=37564) - designer123 (http://www.alteraforum.com/forum/member.php?u=44990) says thats is a problem with the pathlength and i use his workaround. 

 

After that, if i try to simulate i get the errormessage:  

 

# ** Error: (vsim-7) Failed to open VHDL file "altera_sdram_partner_module.dat" in rb mode.# # No such file or directory. (errno = ENOENT)# Time: 0 ps Iteration: 0 Instance: /spotter_qsys_system_tb/new_sdram_controller_0_my_partner# ** Fatal: (vsim-4) ****** Memory allocation failure. *****# # Attempting to allocate 1073741840 bytes# # Please check your system for available memory and swap space.# # # Time: 0 ps Iteration: 0 Instance: /spotter_qsys_system_tb/new_sdram_controller_0_my_partner File: C:/SPOTTER_FPGA_ADC_CONTROL_TEST/SPOTTER_QSYS_SYSTEM/testbench/SPOTTER_QSYS_SYSTEM_tb/simulation/submodules/altera_sdram_partner_module.vhd Line: 69 

 

The file altera_sdram_partner_module.vhd defines on line 69 the file altera_sdram_partner_module.dat as init file for ram initialising. 

I can't find this file and than i replace the file with an other *.dat file in the testbench folder. (i have tried some of them with same result) 

 

 

** Fatal: (vsim-4) ****** Memory allocation failure. *****# # Attempting to allocate 1073741840 bytes# # Please check your system for available memory and swap space.# # # Time: 0 ps Iteration: 0 Instance: /spotter_qsys_system_tb/new_sdram_controller_0_my_partner File: C:/SPOTTER_FPGA_ADC_CONTROL_TEST/SPOTTER_QSYS_SYSTEM/testbench/SPOTTER_QSYS_SYSTEM_tb/simulation/submodules/altera_sdram_partner_module.vhd Line: 69# FATAL ERROR while loading design 

 

I hope somebody can say how i can run the simulation. Or where to find the altera_sdram_partner_module.dat or the right one for me. 

 

Thanks 

 

schlittk
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Altera_Forum
Honored Contributor II
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Did you ever get a resolution for this? I'm getting the exact same thing. I'm thinking of trying to trick it with another file.

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