Using:
5M570 Max V CLPD speed grade 5.
CLK_IN is and in port
div_clk(3 downto 0) is a signal
I have a clock that is derived from a counter to provide divide by 4 functionality, and other prescaler divisions. An input clock CLK_IN is on one of the dedicated clock pins and is synthesized to a global clock in the fitter report. The div_cnt(1) is dividing by 4 and is also used for a clock with a fanout of 129. This is also assigned to a global clock and verified via the fitter after synthesis.
The TimeQuest analyzer is giving me Fmax=17.75MHz for div_cnt(1) and Fmax CLK_IN=238.1MHz. div_cnt(3) has an Fmax=105.3MHz fanout of 6 also a global clock.
If I change all instances of div_cnt(1) in all they processes with CLK_IN TimeQuest gives Fmax=24.23MHz also with a fanout of 129.
I suspect the slow time of the div_cnt(1) signal is due to the large fanout. The same design was faster with the CLK_IN with the same fanout.
- Is there a buffer issue with the way the div_clk(1) is connected to the global clock bus? It is verified via the fitter that it is a global clock.
- The Max V does not appear to have a PLL or ALTCLKCTRL megafunction?
- Attempts to buffer it they synthesizer just get deleted by the synthesizer. I have one remaining global clock, is there a way to assign the same signal more than one global clock, I can balance the fanout manually by using the two clocks for different process?
I'd be happy with any other suggestions. I have plenty of space left on the device.
