I need to use a gated clock in my S3 design, and have the choice between using the recommended clock gating circuit or a clock enable. If I use clock enable, will that aggravate the routing congestion because clock enables are routed as regular signals or are they routed as clocks on global clock networks.
I would not worry about routing. That's almost never a problem. Also, every design has a ton of clock enables. What you'll find is that you think you made one giant clock enable, but synthesis will take a lot of your D input and move them down into logic combined with your clock enable. Go to the Compilation Report -> Fitter -> Resource Section -> Control Signals and sort on Usage. There will be a lot of clock enables. This is all good, as it makes your design smaller and faster.Also, I'm not sure what clock gating circuit you mean, but the recommendation is to use clock enables instead of gating your clock almost all the time(unless you use the enable on the altclkctrl, which is best when it works, since it uses no extra resources and cuts power down).