Clock missing from Timing Analyzer - Report Setup Summary

[Mikexx]

I have a clock mux along the lines in "ug-qps-03-design-recommendations.pdf"

I have set the output clock to be a Global Clock in the Assignment Editor and I give it's minimum period in the sdc file. I don't get any warnings of this signal in the fitter report. It is sent to an output pin as well as used internally.

However the clock is not mentioned in the Report Setup Summary whereas the other clocks of interest are.

I've tried a couple of variations of changing name and assigning the output clock to the internal name.

Any ideas where I might be going wrong?

[Mikexx]

The issue is not resolved.

The HDMI_TX_CLK clock is present in Timing Analyzer->

  Diagnostic-> Report Clocks

  Diagnostic-> Report Clock Tree

  Diagnostic-> Report SDC

but not in any other category. Not even Datasheet->Report Fmax Summary

[ShengN_Intel]

Possible to provide design for taking a look? May be can provide personally to my working email address.

[Mikexx]

Many thanks for the offer. I have made some changes but still have the underlying problem. I have cut down the design by removing Signal tap etc that is now emailable in a small zip.

I've looked at you profile but I can't see any contact details or any means to email you with the design.

Can you assist?

[ShengN_Intel]

Here is my working email qi.sheng.ng@intel.com

[Mikexx]

Many thanks for your kind offer.

I sent an email of a zipped design that has been cut down to exclude items like SignalTap that take up an extraordinary amount of disk space. I can confirm this compiles and shows the issues.

Now it's fingers crossed on how aggressive the Intel email filters are!

[ShengN_Intel]

Hi,

I didn't receive the design file. Could you provide the design file to me through drive link?

[ShengN_Intel]

Hi,

I had checked the design. Since HDMI_TX_CLK is not source-synchronous, so you wouldn't see the setup and hold.

You can report the delay by Report Path... From put * and To put [get_keepers {HDMI_TX_CLK}] then you'll see the result like below:

Thanks,

Regards,

Sheng

[Mikexx]

Many thanks for looking into this. And apologies for the delay due to personal commitments.

I'm a little confused as other clock signals are global and also generated from a PLL and yet are listed in the setup and old times.

My understanding of a source synchronous system is when the signal source is clocked by a different clock to the destination register?

The design has many registers that are clocked by a global clock, ie a common clock, in this case HDMI_TX_CLK aka TX_PCLK and therefore should all have a common clock topology?

[ShengN_Intel]

Hi,

HDMI_TX_CLK is an output clock. The timing analyzer does not automatically include them in the internal setup timing analysis unless there is a specific output delay constraint.

Without an explicit constraint, the tool may not consider the output clock when analyzing internal data paths since it assumes the clock is external and isn't used for internal synchronization.

By applying source synchronous output constraint (ie. set_output_delay), you effectively guide the timing analyzer to check that the data arrives at the output in sync with HDMI_TX_CLK, and the required setup and hold times are met. As a result, HDMI_TX_CLK will appear in the setup report since it now plays a crucial role in determining whether the output timing meets your design's requirements.

You may check this link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/quartus/exm-tq-ea-ss-out.html for an example of source synchronous output constraint. There're more details in document AN433.

Thanks,

Regards,

Sheng

[Mikexx]

As explained I had changed the design in the design file I gave you such there was an internal clock signal TX_PCLK that went through an IO buffer in an attempt to separate the pin signal HDMI_TX_CLK and the internal clock.

TX_PCLK is what was the old HDMI_TX_CLK. Sorry for any confusion.

[ShengN_Intel]

Hi,

TX_PCLK is a net. In.sdc, you have to use get_nets

create_clock -name {TX_PCLK} -period 6.734 -waveform { 0.000 3.367 } [get_nets {TX_PCLK}]

Thanks,

Regards,

Sheng

[Mikexx]

Many thanks. Brill