I have incorrect Fitter behavior using lpm_divide function.
I will upload full project design if needed, because this problem did not appear when I take the problematic part out from full project.
I will explain the problem step by step with screen shots:
I have placed lpm_divide with lpm_pipeline=0 that direct the fully combinatorial logic division.
Source registers that drive lpm_divide are InUseMul and Denom.
The lpm_divide does division with fully combinatorial.
The division result is captured by destination register named Rate.
Source and destination registers are both enabled every 8 clocks.
Because of this, lpm_divide need combinatorial delay less than 8 clock time.
To express these timing requirements, I have set set_muticycle_path assignment on these paths.
After I compile this project, I got timing error as this screen shot.
Find this setup violation on TimeQuest report.
From node is as depicted, and To node is Rate (Not depicted).
I investigated inside of lpm_divide, selnode node is combinatorial node as I set
lpm_pipeline=0 on lpm_divide. It is OK.
This is post mapping netlist view, selnose node is combinatorial here.
I see no register node inside lpm_divide. It is OK too.
This is post fitting netlist view, selnose node is converted to register node. I think it is illegal behavior of Fit.
The timing violation is reported from this node to Rate node.
I tried many logic assignment on lpm_divide instances to block this conversion as below:
Netlist Optimizations=Never Allow
Automatic Asynchronous Signal Pipelining=Off
Perform Physical Synthesis for Combinational Logic for Performance=Off
Perform WYSIWYG Primitive Resynthesis=Off
The result is only [Netlist Optimizations=Never Allow] does it work.
If I set [Netlist Optimizations=Never Allow] enabled, You can see no errors after fit.
I think some kind of automatic pipelining optimization improperly happens on my problem.
Quartus Prime 18.1.0 Build 625 Standard
What version of Quartus Prime that you were using? What device that you were using?
Can you run a functional gate level simulation to see if the function is incorrect?
Thank you for your help.
I am running Quartus Prime 18.1.0 Build 625 Standard as my previous post.
Device is Stratix V: 5SGSMD8N1F45C2 as see in Project navigator tree.
This project is actual working design ported from Quarts 15.0.
Quartus 15.0 did not produce register node inside lpm_divide.
In 18.1.0 it is working with no problem after I suppressed the register
node generation by doing assignment I mentioned before.
Do you suggest to simulate the register generated version of design work
yes, correct. Running the gate level functional simulation *.vo/*.vho files will help you verify your functionality.
You do not need to run gate level timing simulation because most of the latest device does not support it *.sdo.
1. I do not understand why I need the gate level functional simulation.
If the register inserted version of design works functionally correct,
how I constrain inserted register nodes?
These nodes are currently reported as violation.
2. As I write before, this suspicious behavior happens only in real product design.
I could not reproduce this issue when I take problematic part of design.
Doing gate level simulation on all included design is not realistic.
The project includes EMIF, GXB and others.
3. I am writing the forum here because I was declined from requesting Intel Premier Support.
I do not know why I was declined, but it may cause from company size or so.
There is no place to report Quartus bugs now.
My previous mySupport traffic could not accessible any more.
Please please consider take mySupport back.
4. I am not seeking workaround method or inspecting Quartus behavior.
I am simply reporting Quartus bug I would say.
I expect INTEL to explain why this register insertion occur and if this
behavior is legal, I have to know how to constrain these nodes.
You can still report the bugs here.
you mention that if you take the problematic part of your design out, the issue is no longer there.
Can you compare all the setting that you have in the problematic design vs the non problematic design. If both of the setting are the same, it might be a bugs.
Can you attached your design.qar files here?