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Altera_Forum
Honored Contributor I
1,374 Views

Compilation error: bad path in base.sdc

Hello everyone, 

 

I just installed Quartus Prime Pro 17.1 and the BSP of my board vendor (ReflexCES) of on my machine. I tried a simple compilation but there is a very curious error : a file is not correctly sourced. The error is the following (in quartus_sh_compile.log): 

 

Error (332000): couldn't read file "/opt/intelFPGA_pro/17.1.0_b240/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc": no such file or directory while executing "source /opt/intelFPGA_pro/17.1.0_b240/ip/altera/sld/jtag/altera_jtag_wys_atom/default_jtag.sdc" (file "base.sdc" line 28)  

 

I joined the file base.sdc for the information. The last line is incorrect. It tries to source a file from /opt/intelFPGA_pro ... whereas mys installation path is /media/alban/Secure_HDD/opt/intelFPGA_pro/... (a removable media big enough for the tool). 

I don't get why this path appears here. I searched how this file (base.sdc) is created but did not found anything. 

 

Does anyone knows how to correct the error ? Does it comes from my board vendor ? One should note that I did not installed the update 17.1.2 because the BSP is not yet compatible with it ... :/ 

 

Thanks for the help!
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4 Replies
Altera_Forum
Honored Contributor I
54 Views

I believe the base.sdc file is provided by your BSP. Search your BSP folder. If that file is there, and that hardcoded path also exists in the copy inside the BSP, then the problem is from the BSP. The manufacturer could have incorrectly hardcoded the path, expecting people to install Quartus in the default path. You might be able to manually fix the BSP by editing that file and correcting the path to point to your actual installation directory; however, you should probably still report it to the manufacturer so that they would fix it.

Altera_Forum
Honored Contributor I
54 Views

I found some tcl scripts concerning the base.sdc file in my BSP: 

$ grep --color=always -R "base.sdc" ./ Binary file ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/base.qar matches ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/scripts/base_write_sdc.tcl:# write_sdc base.sdc ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/scripts/base_write_sdc.tcl:# Create base.sdc file from SDC file list extracted from base.sta.rpt. ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/scripts/base_write_sdc.tcl:create_source_from_list "base.sdc" ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/scripts/post_flow_pr.tcl: post_message "Compiling base revision -> exporting SDC constraints to base.sdc!" ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/scripts/qar_ip_files.tcl: set list_in "opencl_bsp_ip.qsf base.qdb base.sdc pr_base.id" ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/tmp_qar_list:base.sdc ./hardware/xpressgxa10_lp1150_v1_ultra_ddr4/top.qsf:set_global_assignment -name SDC_FILE base.sdc  

 

When opening base_write_sdc.tcl, which is probably my best clue, I find : 

# ====================================================================================================================# This procedure create a list of .sdc files found in a .sta.rpt from Quartus compilation.# ==================================================================================================================== proc get_sdc_from_sta_rpt {filename} { list sdc_list set flag0 0 set flag1 0 set flag2 0 set fid while { >= 0} { if { $flag0==0 && ==1} {set flag0 1; continue} if {$flag0==1 && $flag1==0 && ==1} {set flag1 1; continue} if {$flag1==1 && $flag2==0 && ==1} {set flag2 1; continue} if {$flag2==1 && ==1} { break} if {$flag2==1} { set split_line lappend sdc_list ] } } close $fid return $sdc_list } # ====================================================================================================================# This procedure create a file which sources all files passed in argument.# ==================================================================================================================== proc create_source_from_list {filename list} { set fid foreach l $list { puts $fid "source $l" } close $fid } # ====================================================================================================================# Create base.sdc file from SDC file list extracted from base.sta.rpt.# ==================================================================================================================== create_source_from_list "base.sdc"  

 

So I searched for "base.sta.rpt", because I understand that it is the file that creates base.sdc, but it is nowhere to be found ... :/ (except in the previous script).
Altera_Forum
Honored Contributor I
54 Views

Hmm... Double-check your environmental variables to make sure nothing is pointing to "/opt/intelFPGA_pro/17.1.0_b240/". Other than that, I cannot think of anything else. You might have better luck contacting your board manufacturer.

Altera_Forum
Honored Contributor I
54 Views

Already opened a ticket, I did it in parallel ! 

 

Too bad :/  

 

$ env | grep /opt AOC_INSTALL_DIR=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/ ALTERA_ROOT_DIR=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1 AOCL_BOARD_PACKAGE_ROOT=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/hld/board/a10_ref ALTERAOCLSDKROOT=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/hld QUARTUS_ROOTDIR_OVERRIDE=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/quartus INTELFPGAOCLSDKROOT=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/hld QSYS_ROOTDIR=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/quartus/sopc_builder/bin PATH=/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/modelsim_ase/linuxaloem:/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/quartus/sopc_builder/bin:/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/quartus/bin:/media/alban/Secure_HDD/opt/intelFPGA_pro/17.1/hld/bin:/home/alban/local/bin:/home/alban/local/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/games:/usr/games
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