Hi,I'm attempting to use SignalTap II to verify my design is running correctly. I have set the SignalTap signals to be from pre-synthesis to prevent my desired signals from being optimised out. I have set my acquisition clock to be the same clock that drives the changes in my output data. I believe this clock is used in the design correctly because I checked Assignment Editor and found the little 'Status: OK' notification for the signal. My output signal names are black (not red) and and my clock name is also black (not red), and the stp file appears in the project files. In compilation settings, SignalTapII is enabled and points to the correct .stp file. So everything appears to be in working order. However, when I compile and then program via JTAG, I get the 'ready to acquire' notification. I run analysis and then status of the auto_signaltap_0 instance says 'waiting for clock'. My understanding is that means my acquisition clock is not cycling correctly, but I don't know how this can be if the clock in Assignment Editor is confirmed to be OK and found in the design. Because SignalTapII is waiting for the clock to cycle, I guess nothing is triggering at all. Is this a problem with my SignalTap II setup, or my entire project? I know my logic works as I simulated it in ModelSim. Thanks for your time. ap29
--- Quote Start --- Where does the clock come from? --- Quote End --- I assumed it was generated by an oscillator - I found it in assignment editor so thought it was a physical clock. Is it possible that virtual clocks appear in assignment editor? I'm unfamiliar with Quartus in general
What does it mean "found it in assignment editor" ? Did you do the pin assignment of the mentioned clock?You should look into your board reference manual to get the pins reserved for reference clocks.
--- Quote Start --- What does it mean "found it in assignment editor" ? Did you do the pin assignment of the mentioned clock? You should look into your board reference manual to get the pins reserved for reference clocks. --- Quote End --- I think I understand now. In Quartus Assignment editor, I assumed each of the port names were automatically assigned to the pins via some hidden constraints file. If I check the pin planner though, none of them are assigned nodes. There is no link. I will set my clock to a reference clock pin and report back. Thanks