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Altera_Forum
Honored Contributor I
1,336 Views

Compilation incompatibilities Modelsim-Quartus (component conditional generation)

Hello, 

 

We're having some issues while trying to compile a project generated with Quartus 13.1 using Modelsim-Altera Starter Edition 10.1. 

 

The problem is due to a conditional instantiation of the altsyncram component in a .vhd file. With an IF-GENERATE clause we instantiate a dual port ram with dual clock or a dual port ram with single clock, depending on the value of a generic in the entity of the module. For the single clock instantiation we left the signals clock1 and clocken1 => open. This works fine in Quartus. 

 

When we compile this code in Modelsim we get following error: Formal port "clock1" has OPEN or no actual associated with it. We tried different options of the Modelsim compiler and different configurations in modelsim.ini to avoid this error, with no success. 

 

If we connect the signals clock1 and clocken1 to '0', Modelsim compiles it correctly but Quartus gives us the following error: 

 

Error (272006): Connected clock1 port of the ALTSYNCRAM megafunction is unused with the current set of parameters 

 

Looks like Quartus is expecting to have these inputs unconnected and Modelsim expects to bind them to some signal. 

 

Is there a way to define/instantiate this component to ensure compatibility in both Modelsim and Quartus? 

 

Thanks!
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9 Replies
Altera_Forum
Honored Contributor I
85 Views

in the single clock case, have you tried connecting the clock to some internal uninitialised signal?

Altera_Forum
Honored Contributor I
85 Views

 

--- Quote Start ---  

in the single clock case, have you tried connecting the clock to some internal uninitialised signal? 

--- Quote End ---  

 

 

Thank you for your reply. 

Yes, we have tried that as well but Quartus does not accept it either.
Altera_Forum
Honored Contributor I
85 Views

Can you post the code, or a code example showing the same behaviour?

Altera_Forum
Honored Contributor I
85 Views

 

--- Quote Start ---  

Can you post the code, or a code example showing the same behaviour? 

--- Quote End ---  

 

 

The part of code which causes the problem is the instantiation of the altsyncram component: 

 

1. This is the original instantiation which works for Quartus but not for Modelsim: 

 

if_single_clock: 

IF CLOCK_MODE_ID = SINGLE_CLK_ID GENERATE  

altsyncram_component : altsyncram 

GENERIC MAP ( 

address_aclr_b => "NONE", 

address_reg_b => REG_B_CLK, 

clock_enable_input_a => "NORMAL", 

clock_enable_input_b => "NORMAL", 

clock_enable_output_b => "BYPASS", 

init_file => INIT_FILE, 

intended_device_family => DEVICE_FAMILY, 

lpm_type => "altsyncram", 

numwords_a => NUM_WORDS, 

numwords_b => NUM_WORDS, 

operation_mode => MEM_OP_MODE, 

outdata_aclr_b => "NONE", 

outdata_reg_b => "UNREGISTERED", 

power_up_uninitialized => "FALSE", 

ram_block_type => RAM_BLOCK_TYPE, 

rdcontrol_reg_b => REG_B_CLK, 

widthad_a => fcn_max(fcn_log2_ceil(NUM_WORDS),1), 

widthad_b => fcn_max(fcn_log2_ceil(NUM_WORDS),1), 

width_a => DATA_WIDTH, 

width_b => DATA_WIDTH, 

width_byteena_a => 1, 

read_during_write_mode_mixed_ports => RD_WR_MIX_PORTS 

PORT MAP ( 

wren_a => wren, 

clock0 => wrclock, 

clocken0 => wrclocken, 

clock1 => open, 

clocken1 => open, 

address_a => wraddress, 

address_b => rdaddress, 

rden_b => rden, 

data_a => wrdata, 

q_b => sub_wire0 

); 

END GENERATE if_single_clock;  

 

2. Changing the PORT MAP to: 

 

PORT MAP ( 

wren_a => wren, 

clock0 => wrclock, 

clocken0 => wrclocken, 

clock1 => '0', -- or clock1_i 

clocken1 => '0', -- or clocken1_i 

address_a => wraddress, 

address_b => rdaddress, 

rden_b => rden, 

data_a => wrdata, 

q_b => sub_wire0 

); 

 

Makes it compile for Modelsim but not in Quartus anymore. 

 

* Component definition (in case this helps) is: 

 

COMPONENT altsyncram 

GENERIC ( 

address_aclr_b: string; 

address_reg_b: string; 

clock_enable_input_a: string; 

clock_enable_input_b: string; 

clock_enable_output_b: string; 

init_file: string; 

intended_device_family: string; 

lpm_type: string; 

numwords_a: natural; 

numwords_b: natural; 

operation_mode: string; 

outdata_aclr_b: string; 

outdata_reg_b: string; 

power_up_uninitialized: string; 

ram_block_type: string; 

rdcontrol_reg_b: string; 

widthad_a: natural; 

widthad_b: natural; 

width_a: natural; 

width_b: natural; 

width_byteena_a: natural; 

read_during_write_mode_mixed_ports: string 

); 

PORT ( 

wren_a : IN std_logic; 

clock0 : IN std_logic; 

clocken0 : IN std_logic; 

clock1 : IN std_logic; 

clocken1 : IN std_logic; 

address_a : IN std_logic_vector (fcn_log2_ceil(NUM_WORDS)-1 downto 0); 

address_b : IN std_logic_vector (fcn_log2_ceil(NUM_WORDS)-1 downto 0); 

rden_b : IN std_logic; 

q_b : OUT std_logic_vector (DATA_WIDTH-1 downto 0); 

data_a : IN std_logic_vector (DATA_WIDTH-1 downto 0) 

); 

END COMPONENT; 

 

We cannot remove clock1 and clocken1 from the component definition because they are used in the cases CLOCK_MODE_ID = LEGACY_CLK_ID or CLOCK_MODE_ID = DUAL_CLK_ID
Altera_Forum
Honored Contributor I
85 Views

The altsyncram component is declared in the altera_mf library, so a local component is not required. This may be what your problem is, because the component declaration in the altera_mf_componts package has default values for the clocks and clocken if they are left unconnected (ie. left out of the port map, rather than left to open). 

 

Modelsim is correct about the first instance, because "in" ports must be connected to something according to VHDL rules. Quartus is generally a bit more relaxed when it comes to language rules, but modelsim is not. 

 

What you may need to do here is have two if... generates. one for Legacy and one for dual_clk, with a separate ram instantiation in each. 

 

If you post thje full code, I may be able to have a look.
Altera_Forum
Honored Contributor I
85 Views

Thank you for the explanation. 

 

According to your post, the correct way of instantiating this component should be: 

 

USE altera_mf_components.all; -- To avoid the local component declaration which is now removed from code. 

 

And following Port Map, for the ports to be connected to some signal (according to VHDL rules) 

 

PORT MAP ( 

wren_a => wren, 

clock0 => wrclock, 

clocken0 => wrclocken, 

clock1 => '0', 

clocken1 => '0', 

address_a => wraddress, 

address_b => rdaddress, 

rden_b => rden, 

data_a => wrdata, 

q_b => sub_wire0 

); 

 

We already have two if... generates: 

 

1. IF CLOCK_MODE_ID = LEGACY_CLK_ID or  

CLOCK_MODE_ID = DUAL_CLK_ID GENERATE 

where generics are configured for dual clock and clock1 and clocken1 are connected to real signals. This is not causing problems. 

2. IF CLOCK_MODE_ID = SINGLE_CLK_ID GENERATE  

where generics are configured for single clock and clock1 and clocken1 are causing this problem. Now connected to '0' to be strict to VHDL rules. 

 

In this configuration, Quartus reports this error: 

 

Error (272006): Connected clock1 port of the ALTSYNCRAM megafunction is unused with the current set of parameters 

Error (287078): Assertion error: The current megafunction is configured for use with the clear box feature and cannot be used when the clear box feature is disabled 

Warning (287013): Variable or input pin "wren_a" is defined but never used. 

Warning (287013): Variable or input pin "rden_b" is defined but never used. 

Warning (287013): Variable or input pin "data_a" is defined but never used. 

Warning (287013): Variable or input pin "address_a" is defined but never used. 

Warning (287013): Variable or input pin "address_b" is defined but never used. 

Warning (287013): Variable or input pin "clock0" is defined but never used. 

Warning (287013): Variable or input pin "clock1" is defined but never used. 

Warning (287013): Variable or input pin "clocken0" is defined but never used. 

Warning (287013): Variable or input pin "clocken1" is defined but never used. 

 

Some other hints?
Altera_Forum
Honored Contributor I
85 Views

Please post the real code - it is quite difficult to speculate what is going on....

Altera_Forum
Honored Contributor I
85 Views

Actually - this is important: 

Error (287078): Assertion error: The current megafunction is configured for use with the clear box feature and cannot be used when the clear box feature is disabled 

 

Did you generate a netlist for this ram? If thats the case, you need to use the ram as you generated it. If it was generated with 2 clocks, then you need to provide 2 clocks. 

All my suggestions assume you have NOT generated the ram using the megawizard, and are trying to control the ram yourself.
Altera_Forum
Honored Contributor I
85 Views

Sorry, I didn't write the code myself and I'm very new to Altera and Altera's IP cores, so I was not really aware of that. But you are right. 

We finally found a workaround that seems to work for both Quartus and Modelsim. If we DO declare the component ourselves but initialize these two ports: 

clock1 : IN std_logic :='0'; 

clocken1 : IN std_logic :='0'; 

 

And then let them open in the instantiation: 

clock1 => open, 

clocken1 => open, 

 

Modelsim does also compile it (no warnings or errors). 

 

Probably not the best according to VHDL rules but it works for us. 

 

Thank you for your support. 

BR
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