I assume you recompiled from scratch? That causes a whole new place-and-route, which changes the timing on everything in the design. Usually I've seen this when something is unconstrained or incorrectly constrained, and so it still passes timing analysis in both cases, but this "incorrect" portion fails in one and not the other.
You'll want to lock everything down and run SignalTap on that. Hopefully you still have the original design, make a copy of it. Open Assignments -> Design Partition Window and you should see the partition Top(and any others you may have created). Set it's Type to Post-Fit, which will preserver the placement and routing. SignalTap is always in another partition, and so it will be placed and routed around the design that is now locked down. The only major caveat is that you have to use post-fit nodes, because it can't resynthesize. I recommend only tapping registers.
(Note that I'm assuming you've fully constrained the design with timing constraints. If you haven't then I would start there).
