Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16720 Discussions

Compiler Warnings

Altera_Forum
Honored Contributor II
‎12-12-2013 12:03 PM
1,037 Views

I am developing an n linear sorter using n work-items. Therefore, I am using two barrier(CLK_LOCAL_MEM_FENCE) to ensure that compares and shifts are done properly. My code works on FPGAs and GPUs. 

 

I am a bit confused by this AOCL warning:  

 

"Compiler Warning: Threads may reach barrier out of order - allowing at most 2 concurrent workgroups" 

 

 

I thought threads (work-items) reaching a barrier out of order is OpenCL default behaviour or can we assume that on FPGA the work-items within a work-group are always implemented in a lockstep manner? Further, is the compiler trying to implement concurrent work-groups? 

 

 

Thanks
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎12-13-2013 12:13 PM
301 Views

I have met the warning. The work-items within a work-group are not implemented in a lockstep manner, but pipeline (one by one) manner. So, the out-of-order is mainly because of "if-else" statement, when the first work-item(e.g. if) has complex logic and the second work-item(e.g. else) is easy to finish.

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.