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Compiling IPs with the files of /synthesis folder

DYaro1
Novice
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Edit: I'm unsure if this belongs here or to https://community.intel.com/t5/FPGA-Intellectual-Property/bd-p/fpga-intellectual-property

Hello,
My team have a simple file collector that enables us to easily build a project from our own libraries for code reusability. It can collect whatever file we want - .qip or HDL.
Now we need to use the same IP from the IP catalog - I2C master - for different FPGA devices, so it is easier for us to put the generated IP as one of our libraries modules. Also, the same collection system is used for simulation.
Therefore we've decided to collect all of the synthesis HDL files instead, as:
1) .qip files can't be read by our simulation program.
2) .qip match the IP to a specific device (if I'm not mistaken).

The files simulate well, and works
on-board most of the time (We've encountered a problem between I2C master and slave between 2 fpgas, but I'm not sure what is the source).

Nevertheless I'm concerned - does we lose some crucial information on the IP if we feed quartus only it's HDL files?
Is it OK to use the same generated IP over multiple devices this way?
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