Component Editor calculates wrong address size from verilog file

[Altera_Forum]

I have components from 6.x that were working correctly but when upgraded to new 7.2 component do not. 

 Snippet:  I define `define uart_addr_width 3  and use to set the address width in the top level input [`uart_addr_width-1:0] address;  instead of the expected effective [2:0] and size of 3, the SOPC Component signal tab lists a size of 4.  Changing to [`uart_addr_width + 1:0] or [`uart_addr_width:0] also always yields 4. If I change the define, SOPC always reports a value 1 more than the define. Upper/Lower case does not seem to make a difference. The same thing happens on the Data Bus as well.  Hopefully someone has seen and solved this.  Thanks,  Stefan

[Altera_Forum]

Most simple explanation would be, that your definition isn't used cause it's overlayed by another definition. The other point is that changes could be ignored under certain circumstances in a recompilation. I know from VHDL, that changing a default value in a entity generic definition would not take effect unless you force a recompilation by a change in architecture - or simply deleting the db folder content.

[Altera_Forum]

I've been unable to use generics in VHDL and hence hdl_parameters in the TCL to paramterize address widths in SOPC 7.2. I'm afraid that I've found no alternative but to use fixed widths for component ports! Certainly in VHDL. e.g. 

  avs_control_address : in std_logic_vector(2 downto 0);  is OK but ..   avs_control_address : in std_logic_vector(addr_width-1 downto 0);  won't work and SOPC thinks the addr span is always 1 word!! i.e. (0 downto 0) regardless of the addr_width generic/parameter.  This is a real problem and I hope Altera get round to fixing this issue soon.

[Altera_Forum]

FvM - I see the problem in the component editor after I load the HDL file. The tab that lists the signals has the incorrect signal width. I have not added this new component to an SOPC design yet. I listed the addr bus in the example, but the data bus is also effected and generates a component editor warning that the data bus is not 8,16,32 bits wide. I don't think the value is being overwritten as I only define/use it in the top level file and the reported value is always 1 more than the value I put in the define. 

 avemo- I had seen some previous posts about VHDL defines/generics having to be all capital letters to be able to work. I'm not sure if that will solve your problem, but all caps didn't make any difference with verilog.

[Altera_Forum]

I hit a similar problem using Verilog parameters to create SOPC custom components. At the end I changed everything to plain old integers and filed a service request. It's currently flagged for a fix in Quartus 8.0.