Component syntax error - help fast

[Altera_Forum]

COMPONENT DIVIDER IS 

PORT ( NUMERATOR, DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 );  QUOTIENT, REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ));  END COMPONENT;    MODULE2: DIVIDER PORT MAP( DIS_1POS, TOTALTIME * FREQUENCY, VEL_QUO, VEL_REM );   above is the code, here is the errors:   Error (10500): VHDL syntax error at distance.vhd(54) near text "PORT"; expecting "(", or "'", or "." Error (10500): VHDL syntax error at distance.vhd(54) near text ";"; expecting ":=", or "<="   I don't understand what I did wrong... please help me quickly... thanks

[Altera_Forum]

I would recode it as 

 COMPONENT DIVIDER PORT ( NUMERATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); QUOTIENT: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); ); END COMPONENT;  Note each port is a single declaration  I think the "Is" after the component declaration is only valid from VHDL 93, so you need to check that you are compiling for 93 not 87  So for 87 use the following  COMPONENT DIVIDER ... END COMPONENT;  and for 93 use the following  COMPONENT DIVIDER IS ... END COMPONENT DIVIDER;   Also, check you have included the correct libraries atthe start of the file  library IEEE; use IEEE.STD_LOGIC_1164.all;   Hope this helps

[Altera_Forum]

--- Quote Start ---  I would recode it as  COMPONENT DIVIDER PORT ( NUMERATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); DENOMINATOR: IN STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); QUOTIENT: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); REMAINDER: OUT STD_LOGIC_VECTOR ( 9 DOWNTO 0 ); ); END COMPONENT;  Note each port is a single declaration   --- Quote End ---    Actually, now I am not sure if this makes a difference. I always break each port out onto a separate declaration but thinking about it again it should be OK. I reckon it's more likely to be the VHDL 87/93 issue I described

[Altera_Forum]

Your not showing the complete code. The error isn't understandable from this snippet. Also what's error line 54 in the original code?

[Altera_Forum]

Hi, 

 I can see an inferred multiplication on port map. Can you do that?   I think port map is for wiring only. You better do the multiplication somewhere else and preferably in a clocked process.   kaz

[Altera_Forum]

--- Quote Start ---  I can see an inferred multiplication on port map. Can you do that?  --- Quote End ---  Yes, the shown code would be completely accepted by Quartus with use ieee.std_logic_unsigned.all in effect, if appearing at the right place of a design, of course with the required signal and library definitions. I guess, it's just an overall design syntax problem. As said, not understandable from a snippet.

[Altera_Forum]

Hi, 

 However, I see it very odd to infer a mult on an instantiation of a divider...would fellow ModelSim accept it? I doubt it. Note also that the last odd statement in port declaration should not have semicolon(second post).   Kaz

[Altera_Forum]

However, I see it very odd to infer a mult on an instantiation of a divider...would fellow  

--- Quote Start ---  ModelSim accept it? I doubt it.  --- Quote End ---  No ModelSim doesn't accept it. I confess, that I was surprized Quartus does, but I tried.  Also, I wouldn't use positional association, cause it's highly susceptible for parameter mix-up.

[Altera_Forum]

From memory, later versions (perhaps 2000 or 2002) of VHDL do accept operators in a port map. 

 In your port list in the component declaration, I don't think the last port (REMAINDER) should have a semi-colon at the end.