Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Connect external clock via non-dedicated pin to PLL on Cyclone 10 LP

Hi everyone I have a PCB that I cannot change, on which a clock is connected to a non-PLL-dedicated pin. I was indeed trying to use a PLL, but Quartus 20.1.1 Lite software hinders to connect the PLL due to the pin location and puts an error with respect to that. I wonder, because I can connect any pin input to internal logic, I can connect internal logic to CLKCTRL and I also can connect CLKCTRL outputs as PLL inputs, but routing the pin via CLKCTRL to a PLL isn't allowed, too. I expect that there is a software limitation to avoid jitter, but since my clock is only 40 MHz, I am asking for a way to override this limitation, a setting or configuration string. Any help would be appreciated, Stefan
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3 Replies
Honored Contributor III

Do you need to go through the clock control block?  You should be able to connect an internal design signal directly to a PLL input.

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Thanks sstrell,


unfortunately, it seems not possible on Cyclone 10 LP:


If I directly connect the pin to the PLL I get:

Error (176554): Can't place  PLL [...] -- I/O pin [..] (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device


If I add some combinational logic (inverter) I get:

Error (15065): Clock input port inclk[0] of PLL [..] must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info (15024): Input port INCLK[0] of node [..] is driven by [..] which is COMBOUT output port of Combinational cell type node [..]


(I replaced signal names by "[..]")


The latter error message also shows up if I use "pin - inverter - global - pll", although "pin - inverter - global"  is usually valid and plls can be driven by globals.

The check seems to be implemented in Quartus and my question is if there is a way round.



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As per the user guide, the PLL can be driven by a GCLK, but there is still a restriction.

"This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK. An internally-generated global signal cannot drive the PLL."

Referred from note (2) below diagram.

The GCLK network can be accessed by dedicated inputs as mentioned in following page:

As clearly mentioned above, "An internally-generated global signal cannot drive the PLL", so this restriction remains.

One possible way for you is that if there is another PLL in your design, you may try to use that to drive this PLL through clock control block.


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