Connecting bus widths smaller than the port size

[Altera_Forum]

Dear Gurus, 

 Apologies for what I'm about to ask but I can't find anything in the documentation thus far to explain what I need to do.   I have a entity that has 8x8bit ports and reads these ports and squirts the values down a serial line. Two of these ports are used to read a FF_DEPTH[11..0]. So far I have successfully connected FF_DEPTH[7..0] to one port but I don't know how to get the other [11..8] into the other port.   I've tried merging buses, with a temporary 4 bit bus that connected to GND to get try and match bus widths but the results were not as desired. Any help would be appreciated.   Regards,   H

[Altera_Forum]

Are you using schematics or HDL?

[Altera_Forum]

Dear std_logic_vector, 

 I am using Quatus II version 9.0.   Hope this helps,   H

[Altera_Forum]

Hi H, 

 Well, I suppose you're using schematics. Take a look at the attached jpg.  5 segments of the bus are labelled differently. Maybe this can be done easier, but this works for me.  Success, Ton

[Altera_Forum]

You need to split the [11..0] bus into [11..8] and [7..0] by setting the properties of the input ports. You may have to set the source to [11..8], [7..0] but I don't think so. I should work so long as the source has the appropriately numbered bits.

[Altera_Forum]

Hi Folks, 

 Thanks for your help and apologies to SLV for not actually answering your question before but you guessed correctly. I have taken your example and tried the attached, which seems to work.    Is there a way defining which bits go to which (say if you have abus[15..8] connected to aport[7..0] does it always connect the highest bits together in descending order? Don't feel obliged to answer...).    Thanks again for all your input.   Best regards,   H

[Altera_Forum]

If you go to help "How to work with connectors" I think it shows that you can split out individual bits connect them in any order to any bits of another bus that is merged from its individual bits. It also points out that a bus merged say from left to right then it is split from right to left Another thing, you don't have to actually draw the bus from block to block so if your .bdf gets too cluttered you may want to leave out some lines.

[Altera_Forum]

--- Quote Start ---  Hi Folks,   Thanks for your help and apologies to SLV for not actually answering your question before but you guessed correctly. I have taken your example and tried the attached, which seems to work.    Is there a way defining which bits go to which (say if you have abus[15..8] connected to aport[7..0] does it always connect the highest bits together in descending order? Don't feel obliged to answer...).    Thanks again for all your input.   Best regards,   H  --- Quote End ---    Hi H,  You didn't indeed answer my question, but my guess was ok. To swap bit order, you can use a small simple piece of VHDL-code, as attached, including Quartus symbol file. Can also be used to split busses, or to make a bus partially constant, with some minor modifications. Consider this as my gift to the public domain :-) To be used without any warranty.  Cheers, Ton