Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15469 Discussions

Connectivity issues when "Set as Design Partition" is ON in Quartus Prime

EPeet
Beginner
1,018 Views

One of the sub-blocks in the design I am trying to synthesize comes as a pre-synthesized IP (.vqm file).

If I run the synthesis & PlaceAndRoute without any special commands, it works ok.

But as this block has been already pre-synthesized by the vendor, I would like to just insert it without letting the synthesis doing any further optimizations (and also let the ports of the IP survive synthesis). But when I set the "Set as Design Partition" for the IP, the "Partition merge" stage fails; the reason is that a lot of ports of the IP has incorrect connections:

 

Error (35052): Partition "xxx" has port "yyy" driven by a constant connected to the illegal node

 

What am I doing wrong?

0 Kudos
1 Reply
KhaiChein_Y_Intel
94 Views

To avoid constants driving the partition boundary, modify the specified partition assignment. Adding an HDL wrapper and setting the partition assignment on the wrapper level to absorb the constant might avoid the illegal netlist structure.

Reply