I have implemented my own SD host (that is an SD card controller) in VHDL and now I'm struggling to find the right constraining strategy.
The SD bus is made up by:
- SD_CLK: the clock, which is generated by the host
- SD_CMD: bidirectional command/response line (launched on the falling edge, latched on the rising edge of the clock)
- SD_DAT[3:0]: bidirectional data lines (launched on the falling edge, latched on the rising edge of the clock)
The main issue of the SD bus is that the SD clock has variable frequency: it is 100-400 kHz during the initialization phase, it is 25 MHz in normal mode. For this reason, I avoided using a PLL and instead generated the clock by mean of a counter, starting from my internal 50 MHz clock. This way, all the internal signals are launched and latched by the 50 MHz clock, by using a launch enable and a latch enable signal, which are generated by the same process that generates the SD clock.
Now, my difficulty is to find the right way to describe the scenario using the SDC constraints, because internally signals are relative to the main 50 MHz clock, while externally they should refer to the SD clock. I know that multicycle should have a primary role, but I just can't find the right way to do it. Any ideas?