Constraining interface with multiply clocks

[Altera_Forum]

Hi 

I got the following problem: FPGA is controlling DDS (AD9910) driver with internal clock sysclk running at 640 MHz. The spec says that dds control pins are sampled with sys_clk running 1/4 of sysclk = 160MHz and control signals timing should be ts = 1.75ns, th=0 ns, to that clock. FPGA control logic is running at 80MHz ( main FPGA clock got same source as DDS clock, but it goes thru clock buffer device). DDS got special pin SYNC_inp to synchronize its internal clock that should be run with 1/16 of sysclk = 40MHz. I want to generate that signal from FPGA pll to synchronize control signals from FPGA to DDS sys_clk clock.  How should i write the constrains as all 3 clocks of interrest are with different frequencys.  In pll i created 40MHz clock that is shifted 180 degrees compared to 80MHz control logic in FPGA.  create_generated_clock -name DDS_SYNQ_CLOCK_ext -source [get_pins {inst5|m25_pll_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}] [get_ports {DDSA_SYNC_INp}] -multiply_by 4  I used multply by 4 as DDS sampling signal is running at 160MHz ( am I correct)  assuming 0 ns path delays I wrote output delays are:  set_output_delay -clock { DDS_SYNQ_CLOCK_ext } -max 1.75 [get_ports {DDS_CONTROL_SIGNALS [*]}] set_output_delay -clock { DDS_SYNQ_CLOCK_ext } -min 0.0 [get_ports {DDS_CONTROL_SIGNALS [*]}]  my question is Is it correct, should be there any multicycle as DDS_CONTROL_SIGNALS run at 80MHz and they are sampled by external device with 160MHz clock ?

[Altera_Forum]

If I understood your design: you got 80MHz clock sourcing fpga. Then FPGA PLL generates 40MHz and 160MHz for DDS chip. 

I will keep all 3 clocks in phase. And yes your constraints are correct. You can add multicycle of 2 setup/1 hold if indeed your generated signals are every two clock periods of latching clock.

[Altera_Forum]

--- Quote Start ---  If I understood your design: you got 80MHz clock sourcing fpga. Then FPGA PLL generates 40MHz and 160MHz for DDS chip. I will keep all 3 clocks in phase. And yes your constraints are correct. You can add multicycle of 2 setup/1 hold if indeed your generated signals are every two clock periods of latching clock.  --- Quote End ---    Maybe i wrote it too complicated ;p 1. FPGA got 80 MHz source clocking 2. FPGA PLL generates 80MHz signal for internal logic, and 40MHz 180 phase shifted clock for DDS synchro pin 3. DDS got its own 640/160 MHz clock that can be synchronized via 40MHz signal on SYNQ_in pin. 4. DDS timings 1.75ns/0ns are required for internal dds 160MHz signal.  I can see in timequest that when i add -multiply_by x on generated signal in waveform view its phase offset is gone. Anyidea why ? should i add after -multiply -invert or -phase instruction ?

[Altera_Forum]

So basically the DDS 160 clock is not synchronous to fpga clock but is made so through the 40MHz signal. 

Your tSU/tH are relevant to the latching clock (160). You are trying to tell fpga about this 160 clock which is not output by fpga You can either declare a virtual clock or actually generate that clock from PLL for the sake of constraints only(this is legal). Then your constraints will be correct but you might need to adjust if there is clock skew between fpga and dds as clock is not going with data. I am not sure why you change phase to 180(you can do that if it helps timing).