Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.

parallel adder package

Altera_Forum
Honored Contributor II
1,365 Views

I want to create a package which contain 

  • procedure for full adder 

  • procedure for parallel adder using full adder defined in the same package 

 

but there is some error. Please check the source code 

 

 

---------------------------------------------------------- 

library ieee; 

use ieee.std_logic_1164.all; 

-------------------------------------------------------- 

package digital_package is 

procedure full_adder(signal a,b,cin:in std_logic;  

signal s,c: out std_logic); 

procedure parallel_adder (signal a,b:in std_logic_vector(3 downto 0); 

signal cin: in std_logic; 

signal s: out std_logic_vector(3 downto 0); 

signal cout: out std_logic); 

end digital_package; 

------------------------------------------------------- 

package body digital_package is 

procedure full_adder(signal a,b,cin: in std_logic; 

signal s,c: out std_logic) is 

begin 

s<=a xor b xor cin; 

c<=(cin and(a xor b)) or (a and b); 

end full_adder; 

---------------------------------------- 

procedure parallel_adder (signal a,b: in std_logic_vector(3 downto 0); 

signal cin: in std_logic; 

signal s: out std_logic_vector(3 downto 0); 

signal cout: out std_logic) is 

signal t:std_logic_vector(3 downto 0); 

begin 

full_adder(a(0),b(0),cin,s(0),t(0)); 

full_adder(a(1),b(1),t(0),s(1),t(1)); 

full_adder(a(2),b(2),t(1),s(2),t(2)); 

full_adder(a(3),b(3),t(2),s(3),cout); 

end parallel_adder; 

end digital_package; 

-------------------------------------------------------------------------------
0 Kudos
3 Replies
Altera_Forum
Honored Contributor II
538 Views

You didnt post the error, but I suspect its the fact you have a signal declared inside a procedure - this is not allowed.

0 Kudos
Altera_Forum
Honored Contributor II
538 Views

yeah you are right. It shows similar error. 

 

ERROR MESSAGE 

 

Signal declaration t not allowed in this region.
0 Kudos
Altera_Forum
Honored Contributor II
538 Views

Why are you using procedures anyway? entities would be more appropraite

0 Kudos
Reply