Constraint Intern signal that clocks Registers

Altera_Forum · ‎08-02-2010

Hi everybody,

I have recently started to learn how to use timequest tool in Quartus, and i have a question for wich i didn't find answer in litterature.

In my design i have many registers that are clocked by internal signals (so not a clock signals), signals that come from combinatorial logic, and i want to know how should i consider those signals (as a clock or not) when i want to declare them in timequest, and how should i contraint them?

Thanks for your help in advance.

Altera_Forum · ‎08-02-2010

You should not do that in FPGAs (may be ok with ASICs). Clock tree is valuable asset of fpga so use it for clocking registers. The rest of fabric signals are poor quality for any clocking and will cause chaos to RTL chains.

If absolutely necessary then use clock mux or other techniques to join the clock tree.

Altera_Forum · ‎08-02-2010

Ok,

In my case i use a signal that is active when the current state of my fsm is "good" :

if (fstate = WR OR fstate = WR_PUT_DATA)  then 
    data_to_write <=data_in;
end if;

What i did :


wr_fstate <= '1' when fstate  = WR else '0';

And then i have changed the code to got an "Edge" to clock the register:

if wr_fstate'event and wr_fstate ='1' then 
    data_to_write <=data_in;
end if;

And i don't know if that is wrong !

Thank you for your answer :)

Altera_Forum · ‎08-02-2010

What is wrong is creating a clock out of logic. Instead of using it as a clock, use it as an enable on a register clocked from the system clock:


process(clk)
begin
  if rising_edge(clk) then
    if enable = '1' then
      ....do something
    end if;
  end if;
end process;

Altera_Forum · ‎08-07-2010

Ok thank you, i will change all the clocks of my registers then!

Another question, is it safe to make a clock divider without doing any thing else, like specifiying that the signal out of the registers will clock all the other blocks ?

Here is the VHDL code that i use, and it works, but i am not sure that this is the best way to do it, or at least, there are may be some precautions to take.

library ieee;
use ieee.std_logic_1164.all;
entity clk_div is  
port
(
    C : in std_logic;         
    CDIV: out std_logic:='0'
);
end clk_div;
architecture arch of clk_div is 
signal CDIV_t : std_logic :='0';
    begin
    
    PROCESS (C) IS
    BEGIN
        
            IF (C'EVENT AND C='1') THEN
            CDIV_t <= '1' XOR (CDIV_t);
            END IF;
    END PROCESS;
    
CDIV<= CDIV_t;
end arch;

Thank you.

Altera_Forum · ‎08-07-2010

That last block is correct. It will produce CDIV with half of C's frequency.

In TimeQuest, you should add a generated clock constraint for CDIV.

However, as Rsyc was saying, if possible avoid clocks driven by logic.

Instead, prefer using PLLs or using clock enable (as described in Rysc's post).

To be read on ripple and gated clocks: http://www.alteraforum.com/forum/showthread.php?t=2388