working with Quartus 8+Synplify DSP + Synplify PRO

[Altera_Forum]

Hi all, 

 I'm working on a undergraduate final project, and I use SynplifyDSP to implement a video improvement algorithm. The problem I faced - In my algorithm I have to access external memory in between two parts of the algorithm, so to do so I divided my Synplify DSP project into several blocks (in several files), I then synthesized each one separately (firstly I created VHDL in Synplify DSP and then went to Synplify PRO and ran a synthesis there). This have created several VQM's that I then inserted into Quartus.  When I then compile the project, I get errors -  things like undeclared pins etc. I think that this happens because Synplify DSP creates blocks with same names when working on different files.  I tried to combine the entire project into one file, but then when I choose retiming in synplify I didn't get the frequency I need (but when I synthesize each part on its own, I do get it to work fast enough).  My only conclusion - I must find a way to force the SynplifyDSP\PRO to generate different names, so I would be able to combine it all in Quartus, and thus hold the minimum frequency I need.  any ideas on how I can to that?  I would really appreciate any help...  thanks, Bulzeye  P.S. sorry for my English...

[Altera_Forum]

still looking for a solution :(

[Altera_Forum]

try importing a .vqm into a separate QII project and exporting that project's "top" partition as a .qxp. then import the .qxp into your main project

[Altera_Forum]

thanks - I will surely try this! 

didn't know this option before that...

[Altera_Forum]

I tried to do this today -  

I created a Quartus project for each of the parts, synthesized it (I choose to export qxp file post synthesis) I then went to my main project. I couldn't find a way to insert the qxp file without having instance of each one of the blocks - so I created some bdf files (one file per part - each contains the same ports as are in the real implementation, and I just shorted the output ports to GND). I ran the Analyze and elaborate - and then I imported the qxp into each of the parts using the partition import (btw - I have several instances of every part - I just imported to each one of them the same implementation) I wanted to ask - is this the correct way to work with QXP?  I did get every part to hold timing requirement like I need tough...  and then I got to the main problem - After compiling the entire project I got the "Couldn't fit design into device" error - I need to use one DSP block more than I have... this didn't occur when I compiled the entire project before. I tried turning off the option that converts 'mult and add' to dsp implementation in the Synthesis options - still no good. Is there anything else I could try? or I don't have any other options and I must change things in the algorithm itself?  P.S. I'm using GiDEL card - with Altera ep2s180f1020c3  thanks... 

[Altera_Forum]

you need to instantiate the .qxp and wire it up, using a .bdf is fine. 

 1 DSP block short? that's tough. any constant coefficient multipliers you could put into LEs?

[Altera_Forum]

I do multiply by constant coefficients - but I do this in the Synplify project and I'm not quite sure how to force it to implement the multiply in LE's...

[Altera_Forum]

unfortunately i don't know Synplify, but I would try and find out how to force Synplify to implement some of the constant coefficient multipliers in LE instead of DSP. this will save you from revisiting your actual algorithm, and will free up some DSP blocks for future design changes

[Altera_Forum]

--- Quote Start ---  I do multiply by constant coefficients - but I do this in the Synplify project and I'm not quite sure how to force it to implement the multiply in LE's...  --- Quote End ---    Hi,  try the syn_mult_style atttribute in SynplifyPro.  Kind regards  GPK

[Altera_Forum]

thanks! I did manage to fit the design into the FPGA without using this option, but it is nice to know as I'm now using 100% DSP's so this way I could free up some DSP's for the future... 

 Anyway, still having problems - My design is just not working! In SinplifyDSP I get correct results, but when I try it on the FPGA - I get lots of pins stuck at GND.  Using SignalTap I found that it happens after the first block that I did using the above mentioned method. I tried to simulate the vqm in Quartus - and I do get that all my outputs are stuck at GND. No idea why this is... Is it actually possible to simulate vqm's using the Built in Simulator tool? (what I need is actually a logic simulation - just to see that my "1+1" equals "2") And does anyone have any idea why this could happen?  thanks again...  Update: ok - this is weird... I used the option in SynplifyPRO that forces the implementation in LE's - and simulated in Quartus, and now I don't get the stuck at GND outputs...  Is there a problem simulating DSP's?

[Altera_Forum]

--- Quote Start ---  thanks! I did manage to fit the design into the FPGA without using this option, but it is nice to know as I'm now using 100% DSP's so this way I could free up some DSP's for the future...  Anyway, still having problems - My design is just not working! In SinplifyDSP I get correct results, but when I try it on the FPGA - I get lots of pins stuck at GND.  Using SignalTap I found that it happens after the first block that I did using the above mentioned method. I tried to simulate the vqm in Quartus - and I do get that all my outputs are stuck at GND. No idea why this is... Is it actually possible to simulate vqm's using the Built in Simulator tool? (what I need is actually a logic simulation - just to see that my "1+1" equals "2") And does anyone have any idea why this could happen?  thanks again...  Update: ok - this is weird... I used the option in SynplifyPRO that forces the implementation in LE's - and simulated in Quartus, and now I don't get the stuck at GND outputs...  Is there a problem simulating DSP's?  --- Quote End ---    Hi,  Unfortunately I have no experience with SynplifyDSP, only with SynplifyPro and Certify. Is your design functional when you use the LE option ? What is the output of SynplifyDSP, RTL or a kind of gatelevel with DSP blocks ? BTW: Which version of the tools do you use ?  Kind regards  GPK

[Altera_Forum]

I use SynplifyPRO 9.6.1 

SynplifyDSP C-2009.03 SP1 Quartus II version 8 build 231 SP1  SynplifyDSP creates some sort of a VHDL implementation and a SynplifyPRO project (including timing constraints etc).  I then synthesize it in SynplifyPRO to get the VQM file that includes the whole implementation.   Using the LE's the simulation of the block is working, I'm now synthesizing the entire project so I could test it on the FPGA (it takes about an hour of synthesizing...) So I will update as soon as I'll have answers. For me it is really strange that I cannot simulate with the DSP's, but I can with the LE's - or should I say - when using DSP's something is going wrong and not working, but when using the LE's it does work. :confused:

[Altera_Forum]

--- Quote Start ---  I use SynplifyPRO 9.6.1 SynplifyDSP C-2009.03 SP1 Quartus II version 8 build 231 SP1  SynplifyDSP creates some sort of a VHDL implementation and a SynplifyPRO project (including timing constraints etc).  I then synthesize it in SynplifyPRO to get the VQM file that includes the whole implementation.   Using the LE's the simulation of the block is working, I'm now synthesizing the entire project so I could test it on the FPGA (it takes about an hour of synthesizing...) So I will update as soon as I'll have answers. For me it is really strange that I cannot simulate with the DSP's, but I can with the LE's - or should I say - when using DSP's something is going wrong and not working, but when using the LE's it does work. :confused:  --- Quote End ---     Hi,  that are quite old versions of the tools. Maybe you should try newer versions at least for SynplifyDSP and SynplifyPro. Are you using FPGA's which are the first time supported by the tool versions ? My guess is that there is something wrong with the DSP block instanciation in the VHDL file of SynplifyDSP. Maybe you can make a trial by using Verilog  output of SynplifyDSP. For the rest of the flow it makes no difference which language you use.  Kind regards  GPK

[Altera_Forum]

Thanks, I'll try this

[Altera_Forum]

Hi, 

you were right! Using Verilog did helped - the simulation now works as it works when I don't use DSP's at all.  It is strange though - one of the blocks works the same when I implement with DSP's and when with LE's (using VHDL not verilog), but all the others I had to use verilog or LE's only to work :confused:. I guess this is all as a result of some program bugs...  Will wait for the full project synthesis to finish, I hope it would work.  thanks again!

[Altera_Forum]

--- Quote Start ---  Hi, you were right! Using Verilog did helped - the simulation now works as it works when I don't use DSP's at all.  It is strange though - one of the blocks works the same when I implement with DSP's and when with LE's (using VHDL not verilog), but all the others I had to use verilog or LE's only to work :confused:. I guess this is all as a result of some program bugs...  Will wait for the full project synthesis to finish, I hope it would work.  thanks again!  --- Quote End ---    Hi,  I also guess that you run into some tool bugs. That's why I recommend to try newer tool version. On the other hand when your design is running by using verilog maybe you can stay with this solution.   Kind regards  GPK

[Altera_Forum]

The entire project still does not work on the FPGA. It works only in simulation. 

:mad:

[Altera_Forum]

--- Quote Start ---  The entire project still does not work on the FPGA. It works only in simulation. :mad:  --- Quote End ---    Hi,  which output did you use for simulation ?  Kind regards  GPK

[Altera_Forum]

What output are you referring to? 

I used the Verilog implementation, which I converted to VQM, which I then exported as a post synthesis design partition, which I then imported into my main project. Compiled it and loaded to the FPGA.  Simulation - I did in Quartus on the "vqm stage" - using waveform file for the inputs

[Altera_Forum]

--- Quote Start ---  What output are you referring to? I used the Verilog implementation, which I converted to VQM, which I then exported as a post synthesis design partition, which I then imported into my main project. Compiled it and loaded to the FPGA.  Simulation I did in Quartus on the "vqm stage".  --- Quote End ---    Hi,  that means you are running the simulation with the SynplifyPro VQM File. But as far as I understand this only a part of your design. Right ?  Kind regards  GPK

[Altera_Forum]

Yes,you are right.  

 I simulated each part separately - and they worked in simulation. I'm now simulating the entire project (it takes some time)  I also tested the non Synplify related stuff - and they work too .  I have a question - when I update my qxp files - what do I have to do to update them in the main project? What I do now is the following: I delete the "imported partitions" folder in the project library, I then overwrite the old qxp files. In quartus I select all the partitions - right click - import, and I press ok (when "reimport using latest files from previous location" is selected). Is this correct?