Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16836 Discussions

Constraint file for async_fifo macro?

alexislms
Valued Contributor I
409 Views

Where is the constraint file for the async_fifo macro in quartus 23.4?

I get a bunch of CDC timing... why isn't it loaded by default with the module?

Labels (1)
0 Kudos
3 Replies
TingJiangT_Intel
Employee
344 Views

To figure out your question, you are using fifo ip to perform asyn fifo function but there are timing violations in timing analyzer right?

If so can you share your project archived, you can remove your RTL file but please make sure the timing path can be showed in timing analyzer thanks.


0 Kudos
Kenny_Tan
Moderator
319 Views

Not sure if you have update on the above? We will need your design to investigate on this.


0 Kudos
Kenny_Tan
Moderator
258 Views

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



0 Kudos
Reply