Error running TCL script after upgrading from Pro 22.4 to Pro 23.3

[Steven_H]

I’ve attached the files needed to reproduce the error. This TCL script was working in 22.4.

You need to set up Quartus Pro 23.3 environment variables first and then run the following command in the terminal:

quartus_sta -t Synthesis.tcl

Weirdly enough, if I run the same commands in the TCL console in Quartus itself, it has no problem running the “get_names” command. This error is very cryptic as it gives no indication as to why it didn’t work.

[TingJiangT_Intel]

I reproduced the same issue, need some time to figure out this.

[TingJiangT_Intel · Accepted solution]

Hi there, please use the following tcl:

load_package flow

load_package report

#load_package sta

project_new toplevel_Characterization -overwrite

set_global_assignment -name TOP_LEVEL_ENTITY toplevel_Characterization

set_global_assignment -name DEVICE 1SD110PJ1F43E1VG

foreach sfile [list BlockSubsystem.vhd toplevel_Characterization.vhd] {

  set_global_assignment -name VHDL_FILE $sfile

}

set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON

execute_module -tool map

set pin_ids [get_names -filter In* -node_type pin]

foreach_in_collection pin_id $pin_ids {

  set pin_name [get_name_info -info full_path $pin_id]

  set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON

}

set pin_ids [get_names -filter Out* -node_type pin]

foreach_in_collection pin_id $pin_ids {

  set pin_name [get_name_info -info full_path $pin_id]

  set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON

}

export_assignments

execute_module -tool map

execute_module -tool fit -args --plan

project_close

BTW, instead of using quartus_sta, please use quartus_sh -t Synthesis.tcl .

[Steven_H]

Thanks for the response, Ting Jiang.

That resolves the error I'm hitting, but now I hit a new error further down my workflow which is the reason I was using quartus_sta.

Tcl error: ERROR: Quartus Prime Tcl command "create_timing_netlist" is only available for use in the following executables:
quartus_fit
quartus_sta

I need to do a detailed timing analysis along various register paths, but I only need to do the timing on rough synthesis estimates and not a design that is fitted to the FPGA (since we run synthesis many times and I imagine quartus_fit will have a significant time penalty).

Do you have any suggestions?

Steven

[Kenny_Tan]

In your code,

you only run:

execute_module -tool map = running the synthesis

execute_module -tool fit -args --plan = running the fitter and on the plan stage.

You will need

execute_module -tool sta to run on the timing in order to generate the timing netlist.

Here is the documentation that you can refer https://www.intel.com/content/www/us/en/docs/programmable/683432/22-2/tcl_pkg_flow_ver_1-1_cmd_execute_module.html

Thanks,

Best regards,

[Steven_H]

Thanks for the pointer. I've updated my 2-step script to call quartus_sh for synthesis and then quartus_sta on the same project after that when we create the timing netlist and do the timing analysis. I previously had updated both quartus_sta calls to quartus_sh which gave that error. I only should update the first one as suggested.

[Kenny_Tan]

Also,

You should use

quartus_sh -t Synthesis.tcl instead of quartus_sta

[Kenny_Tan]

Not sure if you have further question on this? If no, we shall close this thread.

[Kenny_Tan]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a follow up question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.