Controlling Verilog `define macro with Quartus setting or script

[Altera_Forum]

Some Verilog designs use a `define statement, possibly located inside a file referenced by an `include statement, to control something managed with `ifdef or `ifndef. Instead of using a `define statement, you can define the Verilog macro with a Quartus setting in the .qsf file. You can control the value of the Verilog macro using a script. 

   You can enter the setting through the GUI using "Assignments --> Settings --> Analysis & Synthesis Settings --> Verilog HDL Input --> Verilog HDL macro".  The "Verilog HDL macro" field in the Settings dialog box places the line below into the .qsf file. This line is equivalent to "`define use_input_a 1" or simply "`define use_input_a" in a Verilog file.  set_global_assignment -name VERILOG_MACRO "use_input_a=1"  To add the line to the .qsf without using the GUI Settings dialog box, you can run a Tcl script that has this same line in it. (.qsf lines are also Tcl commands for Quartus.)  I illustrated a scripted solution in controlling_Verilog_define_with_script.zip. I set up the example design to use a Tcl file called my_script.tcl. You edit a line at the top of the script to choose whether to define a Verilog macro called "use_input_a". This Verilog macro is used by my_module.v to select whether input a or input b feeds an assign statement.  My example design checks whether or not use_input_a is defined rather than checking the value it is defined to be. Because my_module.v has an action for the macro being undefined, the script deletes the above line from the .qsf to make use_input_a be undefined. The line below with "-remove" in a script deletes the corresponding line from the .qsf if the line exists.  set_global_assignment -name VERILOG_MACRO "use_input_a=1" -remove  You can run the script manually before compilation with the command below at the operating system command line. Have the Quartus project closed when you run this command.  quartus_sh -t my_script.tcl  The line below in the .qsf will run the script automatically at the start of compilation. I included this .qsf line in my example design.  set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:my_script.tcl"  The PRE_FLOW_SCRIPT_FILE line takes effect only for a full compilation. If you run the steps like Analysis & Synthesis and the Fitter one by one, the PRE_FLOW_SCRIPT_FILE line will not be processed. If you are using another script to run the individual steps like synthesis and fitting, then include either "quartus_sh -t my_script.tcl" or the contents of the my_script.tcl example script inside your compile script before the synthesis step.

[Altera_Forum]

There is another solution when running Analysis & Synthesis from the command line or in a compile script using the quartus_map command. The Quartus handbook shows how to specify Verilog macros on the quartus_map command line. See Volume 1, Section III, Chapter 8 "Quartus II Integrated Synthesis" at Language Support --> Verilog HDL Support --> Verilog HDL Macros.