Counter implementation in Quartus II 7.2

Altera_Forum · ‎04-18-2009

Hi there,

This code http://www.altera.com/support/examples/verilog/ver-counter.html?gsa_pos=5&wt.oss_r=1&wt.oss=counter%20code

results the attached RTL view. I wonder why the Adder is used in this circuit. I would rather expect some T flip-flops. Am I doing something wrong?

Thank you very much in advance.

Altera_Forum · ‎04-18-2009

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I would rather expect some T flip-flops.

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You can only build an asynchronous ripple-carry counter from T flip-flops, almost useless for fast logic design. Or do you see, how the below logic, that describes the said synchronous counter could use T-flip-flops? The adder ist exactly implementing the line result = result + 1;

always @(posedge clk or posedge reset)
  begin
    if (reset) 
      result = 0;		
    else if (ena) 
      result = result + 1;
  end

Altera_Forum · ‎04-21-2009

Ok. Thank you!