How to achieve the global reset function with the modelsim？

[Altera_Forum]

the cpld EPM570T100I5 has the global reset pin, which can reset all registers low when the pin is low.now i simulate my design with modelsim,is there some  

commands or syntax to simulate this function in modelsim？THX！ 

[Altera_Forum]

Hi, 

 I never used chip-wide resets but I assume this input is not visible to firmware but to hardware only(I am not sure, any advice...)  You can emulate an internal reset through logic e.g. a counter going up from 0 to 15 and stop then generate your reset on count values. Make sure the counter powers up at zero and that it is not optimised off.  kaz

[Altera_Forum]

May I also draw your attention to the recent thread "Implementation and timing of reset circuits". 

 kaz

[Altera_Forum]

thank you Kaz

[Altera_Forum]

I don't think you can simulate this with ModelSim, at least not when performing an RTL level simulation. 

 The only way that I can see to do that, would be to add in the HDL code, an async clear to all the registers you are using. Take this async clr signal to the top level, and makes your testbench assert it as the device-wide reset. If you are already using some other async reset signal, combine both the local and wide reset as needed.

[Altera_Forum]

--- Quote Start ---  I don't think you can simulate this with ModelSim, at least not when performing an RTL level simulation.  The only way that I can see to do that, would be to add in the HDL code, an async clear to all the registers you are using. Take this async clr signal to the top level, and makes your testbench assert it as the device-wide reset. If you are already using some other async reset signal, combine both the local and wide reset as needed.  --- Quote End ---    hi,vjAlter! i think i find some way to do this simulation,see the following link: http://www.altera.com.cn/support/software/nativelink/quartus2/eda_pro_advanced_options.html and see 10.b, if you enable the option bring out device-wide set/reset signals as ports, when you start test bench template writer,the generated test bench will add the "devclrn","devpor" in the test bench port map ,like following: frequency_div i1 ( // port map - connection between master ports and signals/registers   .clk(clk),  .clk_100k(clk_100k),  .rst_n(rst_n),  .devpor(devpor_tst),  .devclrn(devclrn_tst) );  // devpor initial begin  devpor_tst = 1'b1; end  // devclrn initial begin  devclrn_tst = 1'b1; end  i tried set the devclrn_tst = 1'b0, all of the registers will be 0, no matter i tried to set it to 1.  but there is no "devoe" signal in the port map, i didn't know why?

[Altera_Forum]

--- Quote Start ---  if you enable the option bring out device-wide set/reset signals as ports, when you start test bench template writer,the generated test bench will add the "devclrn","devpor" in the test bench port map  --- Quote End ---    I think this is only for gate-level simulation, not for RTL level simulation. If you want to perform gate-level simulation, then I understand that would work. Most people use RTL-level simulation only, rarely gate-level.

[Altera_Forum]

--- Quote Start ---  the cpld EPM570T100I5 has the global reset pin, which can reset all registers low when the pin is low.now i simulate my design with modelsim,is there some  commands or syntax to simulate this function in modelsim？THX！   --- Quote End ---   can i get a circuit how to use a reset pin in cpld's?

[Altera_Forum]

you can use the global reset pin, or some global pins as the reset pin.