Create multiple 'Cores' of my design

[Altera_Forum]

Hi, I have a design which does some image processing. I load an input image to a large Block RAM, process it using multiple filters and output it to another block RAM. I also use smaller block rams to buffer the data inbetween the filters.  

 I have designed the top level entity to use just the clock and reset pins as input. would it be possible for me to create multiple copies of this pipeline to run them in parallel? they can all use independent block rams. do i just create a new top level entity and create components for each 'core'? if so will altera automatically handle the creation of the block rams correctly for each copy or will i have to somehow do that separately for each?

[Altera_Forum]

Yes. it's possible. As long as you have enough resources in the device. The question is if you only have clock and reset as an input, how are you loading your block ram? are you just using them as ROMs? 

 Pete

[Altera_Forum]

--- Quote Start ---  Yes. it's possible. As long as you have enough resources in the device. The question is if you only have clock and reset as an input, how are you loading your block ram? are you just using them as ROMs?  Pete  --- Quote End ---    Hi Pete, Yes, I think with my device i might only be able to do maybe 4 such copies but that is ok. the very first block ram which stores my input image is created as a 1-port ROM where i load the data using a .HEX file. The other buffers between filters are all 2-port RAMs with no data initialization. the final block ram is a 1-port RAM also with no data initialization to store my output image.   Is it possible to make copies with my design as is? Or is there some change I can make to my design to allow me to make copies?   thank you!

[Altera_Forum]

a 1 port ram to store the output image doesnt make sense - it means it a write only ram, which would then imply the design has no output. 

 You can copy any design as many times as you like in as many ways as you want, as long as you have enough resources. We have no ideas about the design, interfaces, code or any other design specs so you'll have to start asking some better questions and post some of your code and specs.

[Altera_Forum]

--- Quote Start ---  a 1 port ram to store the output image doesnt make sense - it means it a write only ram, which would then imply the design has no output.  I was going to just write the output to it and then use the in system memory editor to read the image out. I already have the SW version written and working so i just need to compare the output of the VHDL to check.   You can copy any design as many times as you like in as many ways as you want, as long as you have enough resources. We have no ideas about the design, interfaces, code or any other design specs so you'll have to start asking some better questions and post some of your code and specs.  --- Quote End ---    The code is quite long thats why i didnt post it the first time. I did provide the high level details about my design in my original post. are there any other details needed to answer my question? if so i can provide those.

[Altera_Forum]

You first post doesnt really tell us anything other than " it has a some logic with ram buffering between logic stages". This covers just above every FPGA project I have ever seen. 

What are you actually trying to do? You can take your code and just instantiate it multiple times in your top level file...

[Altera_Forum]

--- Quote Start ---  You first post doesnt really tell us anything other than " it has a some logic with ram buffering between logic stages". This covers just above every FPGA project I have ever seen. What are you actually trying to do? You can take your code and just instantiate it multiple times in your top level file...  --- Quote End ---    The actual purpose of my project is to perform edge detection on an input image. thats what the filters are for. the final output gets stored back in memory.   Yes, i understand the general concept that i can instantiate multiple instances of my entity. however, the concern i had was with how Altera IP such as the memory would handle that. I am currently initializing my 1 port ROM with my input image in it using a .HEX file. if i instantiate multiple copies will each copy of the rom start with the .hex file? if so i should be ok. if not, i might have to find a way to move the memory to my top level entity which means i will have to make major changes to my design which i am hoping to avoid doing.

[Altera_Forum]

The cores you created will have parameters about where to get the memory initialisation file from. If you instantiate the same memory over and over they will all take the same initialisation file. 

 How have you created the IP? from the IP catalog or from the megawizard? did you specify the file when you created the memory or have you done it via some assignments settings?

[Altera_Forum]

--- Quote Start ---  The cores you created will have parameters about where to get the memory initialisation file from. If you instantiate the same memory over and over they will all take the same initialisation file.  How have you created the IP? from the IP catalog or from the megawizard? did you specify the file when you created the memory or have you done it via some assignments settings?  --- Quote End ---    No, im just using Altera IP from the megawizard. i specified the file right when i created the memory.