Creating Video Output

[Altera_Forum]

Hello guys! 

 I know, there is a bunch of threads around, speaking of how to create a basic video output, but none of the templates/instructions worked for me. Also I'm quite new to FPGA, Verilog and the whole thing, so I hope you can help me a little further.  First thing: I'm using a Cyclone V GX Starter Kit Devboard.  What I'm supposed to do is creating a video output, based on data from the LPDDR2 RAM, which gets written there by a Nios2 processor.  But let's focus first on a much smaller goal, which I would like to achieve first:  Creating a Testpattern and forwarding the video data to a Clocked Video Output, which sends the data over the onboard HDMI interface. Assuming the onboard AD-whatever HDMI controller is already initialized, I would just have to open QSYS, add those two components with the given parameters, export the conduit of the output and connect it with HDMI data lanes. But nope, it's not that easy! :( First of all, the clocked video output gives me an error about wrong ready latency. Source is 0 and sink 1... Ok, I would insert an Avalon-ST timing adapter and everything is fine, but nope again! There is no timing adapter for video streams :evil: What then? Next to that, how do I connect the conduit of the CVO properly to the HDMI data lanes? I'm assuming that vid_clk is the pixel clok, vid_data is video data as rgb, vid_datavalid is data enable, h/v_sync is h/v sync. But what is vid_h and vid_v for? Where do I need to connect them? I figured out what vid_f is, and since it determines if the video is interlaced or progressive I assume I can leave it unconnected, but the other two?  I would appreciate your help very much, since this is driving me mad for about two weeks now, and I have to come to some results...  Best regards, Migsi