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Critical Delay in TimeQuest Timing Analyzer

Altera_Forum
Honored Contributor II
‎03-19-2008 02:13 PM
1,490 Views

Hello, 

 

I'm trying to identify the critical path of a sequential circuit using the TimeQuest Timing Analyzer. However, I'm facing some dificulties because the tool doesn't provide, as the Classic Timing Analyzer used to do, any table showing the worst-case paths of the circuit. Instead, the TimeQuest generates a table with the Required Width, the Actual Width and the Slack refering to the pulse. 

What is the best way to find the critical delay of my circuit based on the information provided by TimeQuest? 

 

Thanks a lot!
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Altera_Forum
Honored Contributor II
‎03-19-2008 03:06 PM
578 Views

Have you given TimeQuest timing constraints? If you are working with the TimeQuest GUI, there are canned reports in the Tasks pane (double click them to run them), some of which include clock setup. You must have constraints before the reporting commands will display anything. 

 

If you have not constrained your clocks and have a PLL, you can start with "derive_pll_clocks -create_base_clocks". See the documentation to learn how to fully constrain your design.
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