Critical Warning: Synopsys Design Constraints File file not found

[Altera_Forum]

Hello,  

 I’m using quartus for synthesis and place &route. I’m getting the following critical warning: " Critical Warning: Synopsys Design Constraints File file not found: 'smtif.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design"  but I’m using quartus for synthesis too.... what does this critical warning mean?  Thanks,  fina. 

[Altera_Forum]

A assume that smtif is the name of your design? 

It means that you didn't supply a timing constraints file. Without it Quartus can't know what timing the signals should follow, and you have no guarantee your system will work in its environment.

[Altera_Forum]

thanks for your answer!

[Altera_Forum]

So how to deal with it? how to add timing constraints? how to decide how many timing constraints should I add? 

 Thank you very much!

[Altera_Forum]

--- Quote Start ---  So how to deal with it? how to add timing constraints? how to decide how many timing constraints should I add?  Thank you very much!  --- Quote End ---    Hi all,  Please I have the same Critical Warning is there any suggestions or demo that helps me to make timing constrains to my design?

[Altera_Forum]

The most effective solution here is to RTFM, in this case http://www.altera.com/literature/manual/intro_to_quartus2.pdf . Search for TimeQuest, which the warning referred to, and you'll get straight to Chapter 5. 

Consider the handbook as well: http://www.altera.com/literature/lit-qts.jsp .

[Altera_Forum]

Actually, the MOST "most effective solution here" (probably) is to understand that quartus v12 (and possibly other versions, but not v9.0 to my knowledge) has problems accessing files over some networks, like those used by virtual machines for one example. The symptoms are random crashes and more often, claims that this file or that was not found (including default TimeQuest templates) or that you do not have permission to write to some folder that you actually do.  

 So if you were are working with networked files when the OP's error message appeared, try moving the project to a local disk instead and see what happens.  Oh and, AFAIK you do NOT have to create your own timing constraints file, just to get a good compile. A default set of rules will be used.  P.S: imho, a "rtfm" reply is worse than no reply at all. please resist the temptation to patronise people who are simply trying to get a little community help / interaction. such behaviour is hardly welcoming. ask yourself, if all answers could be found by simply "r'ingtfm" then wtf is this forum even here for? 

[Altera_Forum]

--- Quote Start ---  So how to deal with it? how to add timing constraints? how to decide how many timing constraints should I add?  Thank you very much!  --- Quote End ---   I just had the same problem and had been trying to fix it for 2 days, finally done. If you are using Qsys or MegaFunction in your design, the Quartus seems to be very stupid, it will not automatically find the .sdc file by itself, to add them into your design, you have to select Assignment->TimeQuest Analyzer, then in the category find the TimeQuest Analyzer, add the .sdc files generated by Quratus for the IP cores, usually they are located in ../db/ip/submodules/.