Critical Warning: Timing requirements not met

[Altera_Forum]

hi， 

these days,I'm learning timing constraints,and I failed to finish to my work. the reports say,from node “ set_ip_req” to node "set_ip_req_r",the slack is -0.818.the launch clock is 27Mhz，and the latch clock is 100Mhz.Their relationship is about 0.001.clock skew is -0.229,data delay is 0.438.  I have no ideas.how can I solve this? thx:)  oh,have a good night   best regards yang

[Altera_Forum]

A 27Mhz clock and 100Mhz clock are not synchronous to each other. You have to cut timing between them, as there's no way the edges will consistently align. Your design either needs to be able to handle that, or you need a circuit that allows the data to go between(hand-shaking, dual-clock FIFO, etc.)

[Altera_Forum]

--- Quote Start ---  A 27Mhz clock and 100Mhz clock are not synchronous to each other. You have to cut timing between them, as there's no way the edges will consistently align. Your design either needs to be able to handle that, or you need a circuit that allows the data to go between(hand-shaking, dual-clock FIFO, etc.)  --- Quote End ---   ? you mean I can ignore this warning?or use the key word "set timing cut assignment"?

[Altera_Forum]

You can't synchronously pass data between those clocks. A set_false_path would cut them. But you need to determine if that just makes the warning go away and there's still a problem, or if your design can handle an "unknown delay" on this path and work.

[Altera_Forum]

--- Quote Start ---  You can't synchronously pass data between those clocks. A set_false_path would cut them. But you need to determine if that just makes the warning go away and there's still a problem, or if your design can handle an "unknown delay" on this path and work.  --- Quote End ---   27Mhz is the clock that samples signals asynchronously from cpu through an EMI interface.For some reasons,this clock is the main clock domain,and these parameters from CPU are sampled and stored here.while I need to sample some pulses that demand such a clock domain crossing work. and I use two delay latches for sake of metastablity.It seem that is doesn't work well.