Cyclone 10 SERDES Receiver Timing Constraints

[Lakshman-Athukorala]

Hello,

I am trying to send some data serially over a very simple SERDES interface made of a single LVDS clock and data going from FPGA 1 to FPGA 2. 

In the receiver FPGA (FPGA 2), I want to use SERDES without DPA.

My LVDS_CLK is running at 50MHz. The SERDES factor is 8. Therefore my LVDS_DIN rate is 400MHz (50MHz *

I am confused about how to do the timing constraints exactly. I tried to set the input delays using the following :

METHOD 1 :

create_clock -name LVDS_CLK_VIRTUAL -period 20
create_clock -name LVDS_CLK -period 20 [get_ports {LVDS_CLK}]

set_input_delay -clock { LVDS_CLK_VIRTUAL } -min 0 [get_ports {LVDS_DIN[0]}]
set_input_delay -clock { LVDS_CLK_VIRTUAL} -max 0.5 [get_ports {LVDS_DIN[0]}]
set_input_delay -clock { LVDS_CLK_VIRTUAL} -min 0 [get_ports {LVDS_DIN[0]}] -add -clock_fall
set_input_delay -clock { LVDS_CLK_VIRTUAL} -max 0.5 [get_ports {LVDS_DIN[0]}] -add -clock_fall

Timing quest timing analyser does not use my delay value assigned using set_input_delay constraints for some reason. I checked the list of ignored constraints in Timing Quest, but this list was empty, so it was happy with the assignments - just hasnt used them for some reason.

Also, I am not even sure if this method works, as my input clock is only going at 50MHz, while my data is changing at 400MHz. I am not sure if my input delay constraint should be using the virtual clock as I have done here.

Method 2 :

In the IP wizard for the LVDS SERDES, there is this RCCS setting in the Receiver Settings tab. 

Is the correct way to configure the input delay using this RCCS value (and not the SET_INPUT_DELAY constraint)? If so, how does this account for the min and max delay settings? Don't I need two separate settings for the SETUP and HOLD timings to be verified?

Any input is highly appreciated!

Best regards,

Lak

[KennyTan_Altera]

Sorry for the late reply on this, our team are currently looking into this and get back to you as soon as possible.

[ShengN_Intel · Accepted solution]

Hi,

Sorry for delay reply,

Check this https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1/timing.html:

Use the Intel® Quartus® Prime software from version 14.0.a10 onwards to generate the required timing constraint to perform proper timing analysis of the LVDS SERDES IP core in Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.

And this https://www.intel.com/content/www/us/en/docs/programmable/683520/22-1-20-0-1/i-o-timing-analysis.html:

In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path. If there is additional board channel-to-channel skew, consider the total receiver channel-to-channel skew (RCCS) instead of TCCS where .

Now you just need to set the RCCS, then it'll be auto implemented into auto-generated .sdc.

RCCS = (Clock trace delay) - (Data trace delay) + margin

Skew(ps) = (Trace length different in mm) * (propagation delay per mm, typically 5ps/mm for FR4)

For example if your pcb analysis shows that the clock trace is 2mm longer than the data trace:

Skew = 2mm * 5ps/mm = 10ps

Add margin = (e.g. 20ps) = 30ps

Set RCCS to 30ps

Thanks,

Regards,

Sheng

[Lakshman-Athukorala]

Thank you very much Sheng, that makes sense to me!

[ShengN_Intel]

Hi,

If check this https://cdrdv2-public.intel.com/666696/c10gx-51003-683775-666696.pdf

The assigning input delay to lvds receiver part had been removed.

Thanks,

Regards,

Sheng