Cyclone IV GX: Output Skew at DDR LVDS Output

[Altera_Forum]

Hello, 

 my task is to implement a source synchronous interface between a Cyclone IV GX EP4CGX50CF23C6 and an Arria V (B3 ES). Therefore I've read a lot about constraining this (AN433, Altera Webside, Altera Wiki) and even had a look at the online training video but anyhow I am stuck somewhere and totally unsure if I am on the right way.  At our interface the clock is sent together with the data (up to 16 lanes in parallel in each direction) edge-aligned to reduce PLL usage. This all should be done at 200MHz using DDR LVDS to achieve a datarate of 400Mbit per second and pin.  TX: To achieve the lowest amount of skew between data and clock output I also used a DDIO_OUT instance to drive the clock offchip. Driving the clock via a second pll tab is no option as there are no more pll ressources available.  RX: The receiver shifts the clock by +90 degree and clocks the DDIO_IN Megafunction using a seperate RX PLL (source synchronous mode).  Constraints: Here I used the example 32 of AN433 page 38 and adjusted the output_clock to use the DDIO_OUT output for the clock signal. Hopefully this should do the job. The RX is similar to example 56 with edge-aligned input_clock and exceptions added. The allowed skew is +/- 200 ps, so 400 ps in total.  Result: The RX path meets timing with 0.773 ns setup and 0.308 ns hold slack, but the TX path fails timing with negative slack in setup as well as hold timing, -0.118 ns and -0.187 ns.  The RX path looks fine so that should be ok but what can I do to get a better TX performance? All together the total output skew is 705 ps (2 * 200 + 118 + 187). Looking at the datasheet the skew between channels (TCCS) should be less than 200 ps in total or did I get that wrong?  In nearly all guidelines and examples there is a constraint of +/- 100 or 125 ps skew but how can I reach that value or even get near it.  So this is where I am stuck - not sure if there is an error in my constraints or if the cyclone iv is simply unable to drive that high frequency. I did the same on the Arria V and did also fail timing.  Could someone help me?  I attached my example project so one can see what I am doing. Just compile g1.qpf and run report_lvds.tcl in the timequest timing analyzer.   Thank you

[Altera_Forum]

I checked your constraints, and you did both the Rx side and the Tx side properly. Unfortunately, once Altera went to min/max timing analysis (beginning with Cyclone III/Stratix III families), source synchronous output timing has really suffered. It really is just a problem with the micro timing models that are too overly conservative. Since external memory interfaces use the same DDIO components and can run at much higher speeds (and are timed with macro model instead of micro model timing), we know this is a model problem. The best you can do is to keep your output data in the same sub-bank and use the same clock for data and clock (as you've done). It is not unusual to see output data skew at +/- 350 ps because of this problem.

[Altera_Forum]

Many thanks for your reply. I am really happy that my constraints are correct and I know where I stand. But when reading your explanation some other question appeared to me. 

 Is there a way to get proper timing results or other information? Well a Interface between two Cyclone IV GX might work as there is enough receiver skew margin even when the real output skew would be +/-350ps. A smaller value would be better but that is how it is - I can live with that. But how can one get an estimation of the real values. I am asking because I also have a receiver that connot handle the above mentioned +/- 350 ps at its input but may be able to tolerate +/- 150 ps.    So what I keep asking myself is how can I be sure to meet timing if I don't know anything about it except a worst case that will hopefully never appear in the real world since the receiver cannot tolerate it. I don't need an exact value but should I base my calculations on the TCCS Value (anyway, is this the right value?), those typical +/-100ps seen in some application note, any other value, or is there some rule of thumb to get a raw estimate for the actual value.   Thank you and have a pleasat weekend :)

[Altera_Forum]

Unfortunately I know of no way to get a more realistic value for the output skew, and certainly nothing that Altera would stand behind. If I were to take an educated guess, I would estimate that if you keep all the data outputs clocked by the same output clock in the same sub-bank, then you could probably count on around +/- 100 ps.

[Altera_Forum]

Your estimation sounds good and it may approach my requirements. I will have a try at that. 

 Thank you very much indeed!