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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Cyclone IV PCIe hard Ip build failing timing.

Altera_Forum
Honored Contributor II
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I have a build as above that is consistenly failing timing on the coreclock, it 

looks like it's the logic wrapper round the hard IP that's the problem. 

 

I'm about to ask my tame FAE to have a look at it but wonder if anyone else 

has had problems here. 

 

Thanks for any feedback, 

 

Nial.
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