Cyclone IV altgx simulation glitches

[shawn4]

To Whom It May Concern: 

When simulating the ALTGX transceiver Using Questa or Modelsim PE I am seeing glitches on the Tx output waveform. Is this expected? After a rising edge of the data the glitch appears as a narrow pulse 1 serial clock cycle. In the simulation the channel corresponding dout_tx0 has a constant input value.

Thanks,

Shawn

[Kshitij_Intel]

Hi,

Can you confirm that you have a local clean reference clock?

Thank you,

Kshitij Goel

[shawn4]

Hi K**bleep**ij,

 Yes, the reference clock is clean (clk98m_in shown below).

Thanks,

Shawn

[Kshitij_Intel]

Hi,

Is this issue resolved?

Regards,

Kshitij Goel

[Kshitij_Intel]

Hi Shawn,

These are just simulation artifacts, you can ignore them that will not happen in the hardware.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel