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Does the same error occur with Verilog option?
Do you also see the same error with the latest Quartus Pro version 24.1?
Are you using the Siemen Questasim or the Questa Intel FPGA Edition?
Questa Intel FPGA Edition seems to works fine.
Regards,
Richard Tan
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Hello Richard
Many thanks for your answer.
I did rerun the compiler with the Verilog option on and did use Siemens Questasim. It then passes without any errors.
Guess this is the way we have to use the "Simulation Library Compiler" in future.
Regards,
Peter
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Great to hear that. I'm pleased to know that your issue has been addressed.
Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you and have a great day!
Best Regards,
Richard Tan
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