Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your
profile.
I am new with qsys and memory configurations and was wondering if someone could please point me in the right direction. When I generate the DDR3 controller in qsys I get an input called "oct_rzqin" that I do not know what to do with. The DDR3 that I am using (MT41J256M8) has a ZQ pin that is routed to a 240 ohm resistor and then to ground as the spec sheet calls for. It seems like the FPGA oct_rzqin pin is trying to serve the same purpose but I cannot find anywhere if this is necessary or how to properly use it. The design will not compile if this pin stays unconnected. Thanks.
The "oct_rzqin" is not a wire to be bounded to the DDR3, but rather to a rzqin pin of your board. (look for it in the pinout list of your board) (Cyclone V GX Dev Kit : PIN_AK13) regards,
