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Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Cyclone V Development kit with MATLAB HDL Coder Error

Sawicki
Novice
766 Views

Iam following Mathworks guide on HDL coder. But in HDL Workflow Advisor project creation under Embadded System Integration task that I launc. First errors that I get are:

 Warning: hps_0.f2h_irq0: Cannot connect clock for <b>irq_mapper.sender</b>
 Warning: hps_0.f2h_irq0: Cannot connect reset for <b>irq_mapper.sender</b>
 Warning: hps_0.f2h_irq1: Cannot connect clock for <b>irq_mapper_001.sender</b>
 Warning: hps_0.f2h_irq1: Cannot connect reset for <b>irq_mapper_001.sender</b>

I tried changing HDL Code Generation Settings to Verilog instead of VHDL but nothing changed. Also changed Windows 10 system language to English(US). Iam using Quartus 19.1 and got Cyclone V libraries instaled. OS: Windows 10, Matlab R2021a.

Iam including error log file

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Sawicki
Novice
734 Views

Fixed the issue. The solution steps are:

>Using Intel Quartus Prime 19.1 (patched)

>Instaling ubuntu 18.04 LTS and manualy instaling WSL, make and dos2unix (after updating apt package list)

>Enabling WSL in windows control panel

 

(Due to spam system this is pretty much copy of my other post - sorry for spam, solution is the same)

 

 

View solution in original post

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Sawicki
Novice
735 Views

Fixed the issue. The solution steps are:

>Using Intel Quartus Prime 19.1 (patched)

>Instaling ubuntu 18.04 LTS and manualy instaling WSL, make and dos2unix (after updating apt package list)

>Enabling WSL in windows control panel

 

(Due to spam system this is pretty much copy of my other post - sorry for spam, solution is the same)

 

 

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