Cyclone-V RAM Block

[aehsan]

Hi,

I am working on existing FPGA project. In the project, RTL instantiates the ASIC memory models. Along with the project there are qip files for memories. My question is how the ASIC memory models are replaced by the qip files?

Thanks,

[ShengN_Intel · Accepted solution]

Hi,

Check these two links https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/reference/glossary/def_qip_file.htm and https://www.intel.com/content/www/us/en/docs/programmable/683609/23-4/files-generated-for-systems.html to understand the functions of the .qip file. Can double-click the .qip file to check all the respective paths included.

Thanks,

Best Regards,

Sheng

[aehsan]

Hi Sheng, 

Thank you for the answer.  I also found the files I was looking for. 

Thanks,