Cyclone V Transceiver .QIP and .SIP - Do I Really Need Them

[Altera_Forum]

I have generated a Cyclone V transceiver using the QuartusII Megawizard PlugIn Manager which has generated various output files including a .QIP and a .SIP both of which have been added to my QuartusII project files. I would like to manually embed the Cyclone V transceiver in to my own VHDL and do away with the megawizard generated outputs. My question is, can I remove the .QIP and .SIP files and still place and route the Cyclone V transceiver? 

 Interestingly the .QIP has the following entry: set_global_assignment -name SYNTHESIS_ONLY_QIP ON So I was thinking that the .QIP and .SIP is only used for simulation purposes which I have control using Modelsim anyway.  Any help here is much appreciated prior to me ripping it out and finding out the hard way :oops:

[Altera_Forum]

In general you can delete the .qip and .sip files. However, sometimes you need the .qip file, eg., when that file contains the paths to the components that are used to make up the component you're actually using. I'd recommend moving the .qip file, removing it from your Quartus project, and then trying to synthesize. If that works, then you're good-to-go! 

 The other way I sometimes do this, is use the MegaWizard to create an instance, and then look at the generated code. If the code just creates an instance of a component, then you can copy the body of the generated code into your code, clean it up, and use it directly. This is a good way to get consistent generics settings.  Cheers, Dave

[Altera_Forum]

The QIP file is pointing to multiple Verilog/SystemVerilog files that have been created in my design from the Megawizard but this couldn't be required by the synthesis as the Cyclone V transceiver is hard IP on the silicon, I think this is my confusion - what are these generated files for? 

 You are probably right and just trying it and see if I get any errors during the compilation. I wanted to clean up multiple transceiver components generated i.e. transceiver, reset controller and reconfiguration controller in to a single custom VHDL file so that it is all wrapped up nicely.

[Altera_Forum]

--- Quote Start ---  what are these generated files for?   --- Quote End ---   My guess is to confuse the end user :)  I find Altera's generated IP extremely frustrating. The wizard produces a whole bunch of junk from which you have to reverse-engineer which files are actually worth keeping ...  Anyway, keep up the fight! :)  Cheers, Dave

[Altera_Forum]

Just an update on this as I have now had time to play around with this. 

 For the Cyclone V native phy transceiver you do need to include the MegaWizard generated Verilog/SystemVerilog files for synthesis :confused:. I modified the .qip file (also generated by the MegaWizard) to include the transceiver and reconfiguration controller for the transceiver, the .qip file is added to the Quartus project. All the other MegaWizard generated files with the exception of the HDL entity and simulation files were removed.