DAC with THDB-ADA on DE2-115

[Altera_Forum]

Hi there, 

I'm working with DAC on the daughter board THDB-ADA. The pin assignments are correct, I believe, but the circuit doesn't seem to be working. Here are my waveforms from ModelSim, can somebody give me some suggestion on what I did wrong? https://www.alteraforum.com/forum/attachment.php?attachmentid=6876  fyi: I create the data output to the board from 0-16300-0... (so that it will be a triangle waveform)  I'm still doing and glad to here from you. Thank you, Tan

[Altera_Forum]

If your FPGA output is q[7:0], and signal before DAC is DAC_DA[13:0], try this---------- 

DAC_DA[13:0]={1'b0, ~q[7], q[6:0], 5'b00000}  ---------------------------------------------- I contect with technical support of THDB-ADA board. They said this board does not support DC output. I think maybe that means, if you want to get a rectangle like waveform, the shape of that will degrade or change.

[Altera_Forum]

Thank you very much :) 

I'm think I know about this daugher board really well right now :) The reason why this board doesn't receive the DC signal is that, if you have a look at the supplied schematic, there is a high pass filter (parallel RC) at every input. I calculated it to be 1.592 KHz. So, if someone would like to deal with voice frequency, they have to build a frequency amplifier interface. The reason why I didn't get this to be solven before is that I was blindly believe their schimatic, in which the output-bit enables are inputs from that daughterboard, lol. By the way, I'm using VHDL, not Verilog :D We can discuss about this board if you like :)  Regards, Tan

[Altera_Forum]

I am so glad that there's someone who are working with this daughter board as well and so nice to share experence with me. So, thank you very much. 

This daughter board really confused me a lot. I am designing an OFDM communication system using DE2-115 FPGA and THDB-ADA daughter board. I thought I can use this daughter board to convert 8 bit parral signal to multi-amplitude annalog signal. But I found the output waveform are not rectangle like. Nowadays, I want to add the ADC in this daughter board to see I can can get the same signal after DAC and ADC. But I am not sure whether it can work.  BTW, I am using Verilog and my circuit knowledge is so poor that I sometimes cannot understand the schimatic.

[Altera_Forum]

I don't know much about OFDM. As far as I know, it's a system using many sub-carriers to transmit digital information. In case of that, I dont think it is impossible to get multiple frequency signals onto processing by that daughter board. However, the frequency for a carrier using DE2-115 for that ADC abd DAC, in my opinion, are, should be less than 6MHz to create a good waveform. 

Here is a trick that I found myself (I'm sure there are at least 1 more using OBUF) that will be useful for you to deal with ADC and DAC on that board. First, you create 2 25MHz clock by detectting the rising edge and falling edge of your main clock, like: If risingedge, clockR = not clockR If fallingedge, clockF = not clockF Then use your clockF to drive the DAC clocks, Write signals, using clockR to drive ADC and the whole program. This is to avoid the clock skew when sometimes ADC samples first and DAC samples later, and vice versa (try to imagine here, I'm not cery good in explaining, try me if you dont understand) Then, I'm sure your waveform will get no any distortion (if the output is clocked in your program) Cheers, Tan

[Altera_Forum]

I also developed an OFDM modem using the DE2-115 and terasic THDB board. I found that the most fool proof method was to look very closely at the pin assignments in the example projects provided with the THDB card, then replicate it perfectly in your project. Once you get the DAC and ADC up and running, it should be fairly straightforward to develop an OFDM module. You must simulate first though. You have almost no hope without simulating first. Do it in a modular fashion. An OFDM MODEM starts with the IFFT. Say you use a 128 subcarrier system, you need to pass to the IFFT 128 real and 128 imaginary samples, one by one. Say you use Binary Phase Shift Keying, each real and imaginary input represents a point on the constellation diagram. For BPSK, each complex point can encode only 1 bit because you set the imaginary input to zero. So you pass in the real input as, say, 1000 or -1000 (in decimal), and the imag input as zero. The IFFT then creates a real and imaginary 128 point time domain waveform which you must multiply by the cosine (for real) and sine (for imaginary) of the carrier frequency. The carrier is easy to generate using a Numerically Controlled Oscillator. Add the two waveforms, filter and send to the DAC. 

 Then, do the reverse process at the receiver (quadrature multiplication etc), input to FFT. You should get out the same as you put in to the IFFT at the transmitter. For coherent OFDM, the information is in the absolute positioning of the received constellation points, but for a number of reasons, you'll get variations in their positioning. To use coherent OFDM, you must try to get perfect timing and correct for rotations in the channel. If you are developing this system alone with little experience, I would recommend using DIFFERENTIAL encoding, where the information resides not in the absolute position of the received points, but in the difference between neighbouring subcarriers.  To offer you hope, however, all the tools for building an OFDM MODEM are in Quartus, but you need to take it step by step, simulate every step of the way and try to overcome problems one by one (at the transmitter: cyc pre insertion, at the receiver: timing (look at Schmidl Cox), demapping (look at Cordic algorithms). It's not an easy task for one person but it *is* possible.

[Altera_Forum]

Hi everyone: 

 I am trying to use the THDB Board to create a DAC. But I have a problem, I can see my square wave.I tried connecting all the jumpers in the configuration that the manual says but it doesn't work. The assignment pin I think is correct. Could you give a hit to use it??  Thank You

[Altera_Forum]

--- Quote Start ---  Hi everyone:  I am trying to use the THDB Board to create a DAC. But I have a problem, I can see my square wave.I tried connecting all the jumpers in the configuration that the manual says but it doesn't work. The assignment pin I think is correct. Could you give a hit to use it??  Thank You  --- Quote End ---    Follow this  your entity should have:  XOUT : out std_logic_vector(13 downto 0); YOUT : out std_logic_vector(13 downto 0); -- adc 14 bit data inputs XIN : in std_logic_vector(13 downto 0); YIN : in std_logic_vector(13 downto 0); -- Setup ADC and DAC DAC_MODE : out std_logic; -- DAC mode, 1 for dual DAC_WRTA : out std_logic; -- Write signal Channel A DAC_WRTB : out std_logic; -- Write signal Channel B ADC_OEA : out std_logic; -- Channel A enable ADC_OEB : out std_logic; -- Channel b enable PLL_OUT_ADC : out std_logic_vector(1 downto 0); PLL_OUT_DAC : out std_logic_vector(1 downto 0)); -- Clock from HSMC  your interface:  --Clock processing---------------------------  process(CLOCK_50)  begin  if falling_edge(CLOCK_50) then  clockF <= not(clockF);  end if;  if rising_edge(CLOCK_50) then  clockR <= not(clockR);  end if;  end process; --DAC and ADC interface----------------------  PLL_OUT_ADC(0) <= clockR;  PLL_OUT_ADC(1) <= clockR;   PLL_OUT_DAC(0) <= clockF;  PLL_OUT_DAC(1) <= clockF;   DAC_WRTA <= clockF;  DAC_WRTB <= clockF;   DAC_MODE <= '1'; -- Dual mode  ADC_OEA <= '0';  ADC_OEB <= '0';  --your outputs YOUT <= YIN;; XOUT <= XIN;  The whole thing should work. Here is pins the assignment  ADC_OEA Location PIN_T25 ADC_OEB Location PIN_T26 CLOCK_50 Location PIN_Y2 DAC_MODE Location PIN_H24 DAC_WRTA Location PIN_H23 DAC_WRTB Location PIN_M25 PLL_OUT_ADC[0] Location PIN_G23 PLL_OUT_ADC[1] Location PIN_G24 PLL_OUT_DAC[0] Location PIN_V24 PLL_OUT_DAC[1] Location PIN_V23 RESET Location PIN_AB28 XIN[0] Location PIN_T22 XIN[1] Location PIN_T21 XIN[2] Location PIN_R23 XIN[3] Location PIN_R22 XIN[4] Location PIN_R21 XIN[5] Location PIN_P21 XIN[6] Location PIN_P26 XIN[7] Location PIN_P25 XIN[8] Location PIN_N26 XIN[9] Location PIN_N25 XIN[10] Location PIN_L22 XIN[11] Location PIN_L21 XIN[12] Location PIN_U26 XIN[13] Location PIN_U25 XOUT[0] Location PIN_D27 XOUT[1] Location PIN_D28 XOUT[2] Location PIN_E27 XOUT[3] Location PIN_E28 XOUT[4] Location PIN_F27 XOUT[5] Location PIN_F28 XOUT[6] Location PIN_G27 XOUT[7] Location PIN_G28 XOUT[8] Location PIN_K27 XOUT[9] Location PIN_K28 XOUT[10] Location PIN_M27 XOUT[11] Location PIN_M28 XOUT[12] Location PIN_K21 XOUT[13] Location PIN_K22 YIN[0] Location PIN_V22 YIN[1] Location PIN_U22 YIN[2] Location PIN_V28 YIN[3] Location PIN_V27 YIN[4] Location PIN_U28 YIN[5] Location PIN_U27 YIN[6] Location PIN_R28 YIN[7] Location PIN_R27 YIN[8] Location PIN_V26 YIN[9] Location PIN_V25 YIN[10] Location PIN_L28 YIN[11] Location PIN_L27 YIN[12] Location PIN_J26 YIN[13] Location PIN_J25 YOUT[0] Location PIN_F24 YOUT[1] Location PIN_F25 YOUT[2] Location PIN_D26 YOUT[3] Location PIN_C27 YOUT[4] Location PIN_F26 YOUT[5] Location PIN_E26 YOUT[6] Location PIN_G25 YOUT[7] Location PIN_G26 YOUT[8] Location PIN_H25 YOUT[9] Location PIN_H26 YOUT[10] Location PIN_K25 YOUT[11] Location PIN_K26 YOUT[12] Location PIN_L23 YOUT[13] Location PIN_L24

[Altera_Forum]

You can use this to simulate a sine wave 2MHz 

  signal datax_s : std_logic_vector(13 downto 0);  constant len : integer := 100;  type data_array is array(natural range len-1 downto 0) of std_logic_vector(13 downto 0);  signal datax: data_array := ( "10000000000000","10111101101010","11101100000100","11111111101111", "11110011110100","11001011001111","10010000000010","01010000111000", "00011101010111","00000010010001","00000110010000","00101000011000", "01100000001010","10011111110101","11010111100111","11111001101111", "11111101101110","11100010101000","10101111000111","01101111111101", "00110100110000","00001100001011","00000000010000","00010011111011", "01000010010101","01111111111111","10111101101010","11101100000100", "11111111101111","11110011110100","11001011001111","10010000000010", "01010000111000","00011101010111","00000010010001","00000110010000", "00101000011000","01100000001010","10011111110101","11010111100111", "11111001101111","11111101101110","11100010101000","10101111000111", "01101111111101","00110100110000","00001100001011","00000000010000", "00010011111011","01000010010101","10000000000000","10111101101010", "11101100000100","11111111101111","11110011110100","11001011001111", "10010000000010","01010000111000","00011101010111","00000010010001", "00000110010000","00101000011000","01100000001010","10011111110101", "11010111100111","11111001101111","11111101101110","11100010101000", "10101111000111","01101111111101","00110100110000","00001100001011", "00000000010000","00010011111011","01000010010101","01111111111111", "10111101101010","11101100000100","11111111101111","11110011110100", "11001011001111","10010000000010","01010000111000","00011101010111", "00000010010001","00000110010000","00101000011000","01100000001010", "10011111110101","11010111100111","11111001101111","11111101101110", "11100010101000","10101111000111","01101111111101","00110100110000", "00001100001011","00000000010000","00010011111011","01000010010101"); -- 2MHz  create_signal_process: process(RESET,clockR)  begin  if RESET = '1' then  datax_s <= (others => '0');  elsif rising_edge(clockR) then  datax <= datax(len-2 downto 0) & datax(len-1);  datax_s <= datax(len-1);  end if;  XOUT <= datax_s;  end process;  XOUT (DAC channel A) should be a sinewave 2MHz

[Altera_Forum]

Thank you very much for your help. I will try to do this. I hope this time it works.

[Altera_Forum]

--- Quote Start ---  Follow this  your entity should have:  XOUT : out std_logic_vector(13 downto 0); YOUT : out std_logic_vector(13 downto 0); -- adc 14 bit data inputs XIN : in std_logic_vector(13 downto 0); YIN : in std_logic_vector(13 downto 0); -- Setup ADC and DAC DAC_MODE : out std_logic; -- DAC mode, 1 for dual DAC_WRTA : out std_logic; -- Write signal Channel A DAC_WRTB : out std_logic; -- Write signal Channel B ADC_OEA : out std_logic; -- Channel A enable ADC_OEB : out std_logic; -- Channel b enable PLL_OUT_ADC : out std_logic_vector(1 downto 0); PLL_OUT_DAC : out std_logic_vector(1 downto 0)); -- Clock from HSMC  your interface:  --Clock processing---------------------------  process(CLOCK_50)  begin  if falling_edge(CLOCK_50) then  clockF <= not(clockF);  end if;  if rising_edge(CLOCK_50) then  clockR <= not(clockR);  end if;  end process; --DAC and ADC interface----------------------  PLL_OUT_ADC(0) <= clockR;  PLL_OUT_ADC(1) <= clockR;   PLL_OUT_DAC(0) <= clockF;  PLL_OUT_DAC(1) <= clockF;   DAC_WRTA <= clockF;  DAC_WRTB <= clockF;   DAC_MODE <= '1'; -- Dual mode  ADC_OEA <= '0';  ADC_OEB <= '0';  --your outputs YOUT <= YIN;; XOUT <= XIN;  The whole thing should work. Here is pins the assignment  ADC_OEA Location PIN_T25 ADC_OEB Location PIN_T26 CLOCK_50 Location PIN_Y2 DAC_MODE Location PIN_H24 DAC_WRTA Location PIN_H23 DAC_WRTB Location PIN_M25 PLL_OUT_ADC[0] Location PIN_G23 PLL_OUT_ADC[1] Location PIN_G24 PLL_OUT_DAC[0] Location PIN_V24 PLL_OUT_DAC[1] Location PIN_V23 RESET Location PIN_AB28 XIN[0] Location PIN_T22 XIN[1] Location PIN_T21 XIN[2] Location PIN_R23 XIN[3] Location PIN_R22 XIN[4] Location PIN_R21 XIN[5] Location PIN_P21 XIN[6] Location PIN_P26 XIN[7] Location PIN_P25 XIN[8] Location PIN_N26 XIN[9] Location PIN_N25 XIN[10] Location PIN_L22 XIN[11] Location PIN_L21 XIN[12] Location PIN_U26 XIN[13] Location PIN_U25 XOUT[0] Location PIN_D27 XOUT[1] Location PIN_D28 XOUT[2] Location PIN_E27 XOUT[3] Location PIN_E28 XOUT[4] Location PIN_F27 XOUT[5] Location PIN_F28 XOUT[6] Location PIN_G27 XOUT[7] Location PIN_G28 XOUT[8] Location PIN_K27 XOUT[9] Location PIN_K28 XOUT[10] Location PIN_M27 XOUT[11] Location PIN_M28 XOUT[12] Location PIN_K21 XOUT[13] Location PIN_K22 YIN[0] Location PIN_V22 YIN[1] Location PIN_U22 YIN[2] Location PIN_V28 YIN[3] Location PIN_V27 YIN[4] Location PIN_U28 YIN[5] Location PIN_U27 YIN[6] Location PIN_R28 YIN[7] Location PIN_R27 YIN[8] Location PIN_V26 YIN[9] Location PIN_V25 YIN[10] Location PIN_L28 YIN[11] Location PIN_L27 YIN[12] Location PIN_J26 YIN[13] Location PIN_J25 YOUT[0] Location PIN_F24 YOUT[1] Location PIN_F25 YOUT[2] Location PIN_D26 YOUT[3] Location PIN_C27 YOUT[4] Location PIN_F26 YOUT[5] Location PIN_E26 YOUT[6] Location PIN_G25 YOUT[7] Location PIN_G26 YOUT[8] Location PIN_H25 YOUT[9] Location PIN_H26 YOUT[10] Location PIN_K25 YOUT[11] Location PIN_K26 YOUT[12] Location PIN_L23 YOUT[13] Location PIN_L24  --- Quote End ---    I tried to test the program. However it doesnt work. I am using the altera DE2 board and the terasic daughter board. I checked the pin assignment. I cant see anything in the output. Could you help me with this???

[Altera_Forum]

--- Quote Start ---  I tried to test the program. However it doesnt work. I am using the altera DE2 board and the terasic daughter board. I checked the pin assignment. I cant see anything in the output. Could you help me with this???  --- Quote End ---    Could you tell me how you set up your design? If I will check the basic operation, I would set it like: Use an SMA cable to connect the ADC channel A to a generator, say you're using a 1V, 500kHz sine wave. Use another SMA cable for the DAC channel A to the osciloscope. Make sure the contact between your THDB ADA to your DE2-115 is HSMC and is firm (pushing it down a bit hard)  If it doesn't work either, check the jumpers on your daughter board. Leave it as default if you've changed something. I'm curently not with my board so I can't check it.  If it doesn't work either, connect the data, XIN, to the LEDS to check if it works. If not, make sure to set the ADC_OEA to 0

[Altera_Forum]

--- Quote Start ---  Follow this  your entity should have:  XOUT : out std_logic_vector(13 downto 0); YOUT : out std_logic_vector(13 downto 0); -- adc 14 bit data inputs XIN : in std_logic_vector(13 downto 0); YIN : in std_logic_vector(13 downto 0); -- Setup ADC and DAC DAC_MODE : out std_logic; -- DAC mode, 1 for dual DAC_WRTA : out std_logic; -- Write signal Channel A DAC_WRTB : out std_logic; -- Write signal Channel B ADC_OEA : out std_logic; -- Channel A enable ADC_OEB : out std_logic; -- Channel b enable PLL_OUT_ADC : out std_logic_vector(1 downto 0); PLL_OUT_DAC : out std_logic_vector(1 downto 0)); -- Clock from HSMC  your interface:  --Clock processing---------------------------  process(CLOCK_50)  begin  if falling_edge(CLOCK_50) then  clockF <= not(clockF);  end if;  if rising_edge(CLOCK_50) then  clockR <= not(clockR);  end if;  end process; --DAC and ADC interface----------------------  PLL_OUT_ADC(0) <= clockR;  PLL_OUT_ADC(1) <= clockR;   PLL_OUT_DAC(0) <= clockF;  PLL_OUT_DAC(1) <= clockF;   DAC_WRTA <= clockF;  DAC_WRTB <= clockF;   DAC_MODE <= '1'; -- Dual mode  ADC_OEA <= '0';  ADC_OEB <= '0';  --your outputs YOUT <= YIN;; XOUT <= XIN;  The whole thing should work. Here is pins the assignment  ADC_OEA Location PIN_T25 ADC_OEB Location PIN_T26 CLOCK_50 Location PIN_Y2 DAC_MODE Location PIN_H24 DAC_WRTA Location PIN_H23 DAC_WRTB Location PIN_M25 PLL_OUT_ADC[0] Location PIN_G23 PLL_OUT_ADC[1] Location PIN_G24 PLL_OUT_DAC[0] Location PIN_V24 PLL_OUT_DAC[1] Location PIN_V23 RESET Location PIN_AB28 XIN[0] Location PIN_T22 XIN[1] Location PIN_T21 XIN[2] Location PIN_R23 XIN[3] Location PIN_R22 XIN[4] Location PIN_R21 XIN[5] Location PIN_P21 XIN[6] Location PIN_P26 XIN[7] Location PIN_P25 XIN[8] Location PIN_N26 XIN[9] Location PIN_N25 XIN[10] Location PIN_L22 XIN[11] Location PIN_L21 XIN[12] Location PIN_U26 XIN[13] Location PIN_U25 XOUT[0] Location PIN_D27 XOUT[1] Location PIN_D28 XOUT[2] Location PIN_E27 XOUT[3] Location PIN_E28 XOUT[4] Location PIN_F27 XOUT[5] Location PIN_F28 XOUT[6] Location PIN_G27 XOUT[7] Location PIN_G28 XOUT[8] Location PIN_K27 XOUT[9] Location PIN_K28 XOUT[10] Location PIN_M27 XOUT[11] Location PIN_M28 XOUT[12] Location PIN_K21 XOUT[13] Location PIN_K22 YIN[0] Location PIN_V22 YIN[1] Location PIN_U22 YIN[2] Location PIN_V28 YIN[3] Location PIN_V27 YIN[4] Location PIN_U28 YIN[5] Location PIN_U27 YIN[6] Location PIN_R28 YIN[7] Location PIN_R27 YIN[8] Location PIN_V26 YIN[9] Location PIN_V25 YIN[10] Location PIN_L28 YIN[11] Location PIN_L27 YIN[12] Location PIN_J26 YIN[13] Location PIN_J25 YOUT[0] Location PIN_F24 YOUT[1] Location PIN_F25 YOUT[2] Location PIN_D26 YOUT[3] Location PIN_C27 YOUT[4] Location PIN_F26 YOUT[5] Location PIN_E26 YOUT[6] Location PIN_G25 YOUT[7] Location PIN_G26 YOUT[8] Location PIN_H25 YOUT[9] Location PIN_H26 YOUT[10] Location PIN_K25 YOUT[11] Location PIN_K26 YOUT[12] Location PIN_L23 YOUT[13] Location PIN_L24  --- Quote End ---     Does this code work for a Cyclone IV? because I have different pin assigments and I'm using the De2-115 board and the data conversion HSMC.

[Altera_Forum]

--- Quote Start ---  Does this code work for a Cyclone IV? because I have different pin assigments and I'm using the De2-115 board and the data conversion HSMC.  --- Quote End ---    That works for DE2-115 (Cyclone IV, for more specific, Cyclone IV EP4CE115F29C7N) using HSMC THDB ADA

[Altera_Forum]

Hi , 

 I have to interface my Cyclone 3 starter kit with my ADA_thdb board. Can anyone tell me how to proceed with? Are there any sort of constraints or specific things to be noted while interfacing the two boards. I do not wish to spoil my board by programming it in a wrong way.  So any guidelines on how to start with will be appreciated.  Please do enlighten this beginner.  Thanks in advance.

[Altera_Forum]

I don't have a Cyclone 3 board here. I'm not sure what is your interface between the FPGA board and the daughter board. Is it HSMC or GPIO? Can you upload the pictures or give me the web links of your boards? 

First, use the FPGA board manual to obtain the pins for your interface. Make sure you can make a correct pins assignment. Second, try the program I wrote above.

[Altera_Forum]

--- Quote Start ---  I don't have a Cyclone 3 board here. I'm not sure what is your interface between the FPGA board and the daughter board. Is it HSMC or GPIO? Can you upload the pictures or give me the web links of your boards? First, use the FPGA board manual to obtain the pins for your interface. Make sure you can make a correct pins assignment. Second, try the program I wrote above.  --- Quote End ---     Hi duytan ,  Ya sure , I am attaching the pics of the ADA borad .

[Altera_Forum]

--- Quote Start ---  I don't have a Cyclone 3 board here. I'm not sure what is your interface between the FPGA board and the daughter board. Is it HSMC or GPIO? Can you upload the pictures or give me the web links of your boards? First, use the FPGA board manual to obtain the pins for your interface. Make sure you can make a correct pins assignment. Second, try the program I wrote above.  --- Quote End ---     Hi duytan ,  Ya sure , I am attaching the pics of the ADA borad . It is the HSMC board , the first one in the attached pdf. And ya, i'll refer to the pins and keep the assignments ready. Will you be able to verify them for me?  Cyclone 3 Starter board link is here.  http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html   Thanks !

[Altera_Forum]

Pins assignment for Cyclone 3 Starter Board 

Assign this and try my code above  ADC_OEA Location PIN_T3 ADC_OEB Location PIN_R3  CLOCK_50 Location PIN_B9 DAC_MODE Location PIN_L1 DAC_WRTA Location PIN_T24 DAC_WRTB Location PIN_W25  PLL_OUT_ADC[0] Location PIN_V18 PLL_OUT_ADC[1] Location PIN_U18 PLL_OUT_DAC[0] Location PIN_C14 PLL_OUT_DAC[1] Location PIN_D14  RESET Location ==> Choose one of your switch  XIN[0] Location PIN_N13 XIN[1] Location PIN_M13 XIN[2] Location PIN_N6 XIN[3] Location PIN_M6 XIN[4] Location PIN_R18 XIN[5] Location PIN_R17 XIN[6] Location PIN_M14 XIN[7] Location PIN_L13 XIN[8] Location PIN_M17 XIN[9] Location PIN_L16 XIN[10] Location PIN_L18 XIN[11] Location PIN_K18 XIN[12] Location PIN_G18 XIN[13] Location PIN_G17  XOUT[0] Location PIN_T1 XOUT[1] Location PIN_N7 XOUT[2] Location PIN_N8 XOUT[3] Location PIN_J13 XOUT[4] Location PIN_N10 XOUT[5] Location PIN_N11 XOUT[6] Location PIN_K17 XOUT[7] Location PIN_P11 XOUT[8] Location PIN_B2 XOUT[9] Location PIN_B1 XOUT[10] Location PIN_G2 XOUT[11] Location PIN_G1 XOUT[12] Location PIN_K2 XOUT[13] Location PIN_K1  YIN[0] Location PIN_T18 YIN[1] Location PIN_T17 YIN[2] Location PIN_R4 YIN[3] Location PIN_R5 YIN[4] Location PIN_P18 YIN[5] Location PIN_P17 YIN[6] Location PIN_L15 YIN[7] Location PIN_L14 YIN[8] Location PIN_M18 YIN[9] Location PIN_L17 YIN[10] Location PIN_H18 YIN[11] Location PIN_H17 YIN[12] Location PIN_E18 YIN[13] Location PIN_E17  YOUT[0] Location PIN_M3 YOUT[1] Location PIN_T2 YOUT[2] Location PIN_H15 YOUT[3] Location PIN_H16 YOUT[4] Location PIN_N16 YOUT[5] Location PIN_N15 YOUT[6] Location PIN_R16 YOUT[7] Location PIN_T16 YOUT[8] Location PIN_C2 YOUT[9] Location PIN_C1 YOUT[10] Location PIN_H2 YOUT[11] Location PIN_H1 YOUT[12] Location PIN_K5 YOUT[13] Location PIN_L5

[Altera_Forum]

Hi tan, 

 I am currently creating a spread-sheet for the pin assignments. Well thanks a lot! i'll verify my assignments with what you have sent. I have another doubt,  The ADA board feature list mentions the following:  The feature set of the ADA is listed below:  1. Dual AD channels with 14-bit resolution and data rate up to 65 MSPS  2. Dual DA channels with 14-bit resolution and data rate up to 125 MSPS  3. Dual interfaces include HSMC and GPIO, which are fully compatible with Cyclone III Starter  Kit and DE1/DE2/DE2_70/DE2_115/DE3/DE4, respectively  4. Clock sources include oscillator 100MHz, SMA for AD and DA each, and PLL from either  HSMC or GPIO interface  5. AD converter analog input range 2V p-p range.  6. DA converter output voltage range 2V p-p range.  7. DA and AD converters do not support DC signaling    The entire board operates on DC-signaling if am not wrong, as our board is powered by an adapter. So what does it exactly mean by   DA and AD converters do not support DC signalling?  Also i think there is a mistake in the pins wrt_a and wrt_b as there is no pin such as T24 and W25 available.   Am attaching the schematics of Cyclone 3 Starter Board for your reference.  thanks!  ivads

[Altera_Forum]

If you are quite familiar with ADC and DAC, you will see that we need to adjust the gain value which is to adjust the converter into the amplitude of our signal. Well, don't mind if you don't understand what I've just said. I'm not a good explainer. 

In other words, a signal source usually includes DC and AC component. It's like you have a sine wave but it is shifted up or down around the zero. It is because that sine wave is added to a DC component. That is very "annoying" in signal processing as it consumes power when processing, causing heat, reducing the accuracy of the represented binary, adding truncating noise to your signal when processing. Any way, that statement means, you can only put AC signal into you SMA cable (for ADC) and create an AC signal (DAC) Also, when you apply the signal onto your daughterboard, your DC component will be filtered out.  And by they way, I dont think you broke your board, it's maybe because of the contact between your board and daughterboad was not tight. Try to push them toghther harder