I am trying to simulate the Intel DCFIFO IP in modelsim, and have used quartus to generate the IP and simulation vhdl files. The device family is Cyclone 10 gx, which is claimed as supported in the IP documentation.
When running a simulation with a mixed width fifo (16 bit in, 128 bit out), Modelsim exits with the following error:
# ** Fatal: (vsim-3420) Array lengths do not match. Left is 128 (127 downto 0). Right is 16 (15 downto 0).
# Time: 0 ps Iteration: 0 Process: /dataformatteraxififo_fifo_1910_mh5lrga/dcfifo_mixed_widths_component/line__48405 File: /home/tools/altera/17.0/modelsim_ae/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd
# Fatal error in Architecture behavior at /home/tools/altera/17.0/modelsim_ae/linuxaloem/../altera/vhdl/src/altera_mf/altera_mf.vhd line 48407
This happens immediately also when even simulating the IP standalone.
Changing the intended_device_family to "Stratix" doesnt seem to cause this issue, and if I leave the intended_device_family as "Cyclone 10 GX" and intead change the input/output widths to match I get the following error:
# ** Error: Error! Illegal INTENDED_DEVICE_FAMILY.
I am running Modelsim- Intel FPGA Edition 10.5b, and have generated the IP using Quartus Prime 21.1
I have attached the generated sim .vhd file that I was testing standalone which produces the error.
Does anyone know if this is a known bug? or intended behaviour?
Device family Cyclone 10 GX is supported on simulation tool Modelsim 10.5c instead of 10.5b.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.